Abstract: In an outboard marine drive including a vertically oriented engine, a disk member is attached to a lower end of the crankshaft of the engine, and the upper end of the drive shaft is disposed coaxially with respect to the crankshaft and at a prescribed distance from the disk member so that a direct coupling member and an centrifugal clutch device may be interchangeably installed between them. The disk member is provided with axial holes for either pivotally supporting clutch shoes or fixedly attaching the upper end of the direct coupling member. The lower end of the direct coupling member and the clutch drum of the centrifugal clutch device are provided with an identical coupling arrangement for coupling with an upper end of the drive shaft.

Abstract: An IGFET with a gate electrode and insulative spacers in a trench is disclosed. The IGFET includes a trench with opposing sidewalls and a bottom surface in a semiconductor substrate, a gate insulator on the bottom surface, a gate electrode on the gate insulator, and insulative spacers between the gate electrode and the sidewalls.

Abstract: A control circuit is provided to minimize the charging cycle time of a battery charging system by maximizing the length of time that high constant charging current is applied to a discharged battery. The control circuit includes a constant current (CC) error amplifier, a constant voltage (CV) error amplifier, an output amplifier, and two pole-splitting compensation networks. The control circuit works in conjunction with a power source to charge a secondary battery. The pole-splitting compensation networks allow the CC, CV, and output amplifiers to be configured for high gain, without sacrificing output stability. The control circuit provides a sharp transition between the CC mode and CV mode of operation. In the CC mode, fast bulk battery charging is provided. In the CV mode, the control circuit initially provides a "top-off" charge to the battery and subsequently safely maintains the battery at its fully charged state.

Abstract: An impulse radar system useful, for instance, for ground penetration provides three dimensional images of targets. The radar system includes an antenna array with an arrangement of elements that is irregular so that the spacing between elements is different, thereby minimizing redundancy of path geometry between the array elements and the target. This feature reduces unwanted array sidelobes. The radar system incorporates circuitry which permits the utilization of each array element as either a transmitter or receiver antenna element. This dual utilization increases the effective number of elements in the antenna array, providing increased gain and system resolution. The radar system receiver utilizes multiple antenna array receiver elements, each of which is connected sequentially, through a solid state switch, to a single analog to digital converter, thereby providing a digitized signal for processing and display.

Abstract: A patterned planarized insulating layer and a patterned metal layer form all local interconnects required within six-transistor SRAM cells. Supply voltage and ground lines are formed in the metal layer or in a separate layer to maximize available wiring area. Local interconnect size is maximized to increase node capacitance within the cells and reduce soft error rates, and supply voltage and ground wiring area is maximized for added cell stability and static noise margin improvement. Openings in the insulating layer for contacts, including local interconnects, bit lines, supply voltage and ground contacts, are formed with a single mask and self-aligned contact etch. Line size and spacing for the patterned metal layer is minimized because surface contours do not disturb masking and etching and all openings are formed using a single mask. The metal layer can be made thin so that the layers overlying the interconnect layer are nearly flat and so bonding pads in the metal layer are eliminated.

Abstract: A semiconductor chemical vapor deposition reactor includes a susceptor and a cover above the susceptor to reflect and radiate heat from the susceptor back onto the top surfaces of the wafers held on the susceptor, thereby minimizing temperature gradients on the wafers and reducing slip. The cover has an opening in the center through which process gases are injected, creating a Bernouli effect to draw the process gases between the cover and susceptor, where the process gases then deposit on the wafers secured thereon.

Abstract: An article holder generates a gas flow (for example, a vortex) to hold the article at a predetermined distance from the body of the holder. Pins extend from the body of the holder and physically contact an article surface to impede the article movement along the surface. As a result, the article is prevented from bumping against the locator pins surrounding the article when the holder accelerates.

Abstract: A transmitting unit of a wireless security system having randomized successive ("rolling") verification codes transmits a different synchronization code each time that the transmitter unit is powered up. After power up, a pseudo-random value is generated by a pseudo-random number generator. The pseudo-random value is at least in part dependent upon a manipulation of a manually-operable switch of the transmitting unit. The pseudo-random value is incorporated into the first synchronization code transmitted after the first power up. If power to the transmitting unit is then interrupted and then resupplied, for example by removing and then replacing a battery, then the pseudo-random number generator generates another pseudo-random value, the value again depending at least in part upon a manipulation of the manually-operable switch. The pseudo-random value is then incorporated into the first synchronization code transmitted after the second power up.

Abstract: A local interconnect (LI) structure is formed by forming a silicide layer in selected regions of a semiconductor structure then depositing an essentially uniform layer of transition or refractory metal overlying the semiconductor structure. The metal local interconnect is deposited without forming in intermediate insulating layer between the silicide and metal layers to define contact openings or vias. In some embodiments, titanium a suitable metal for formation of the local interconnect. Suitable selected regions for silicide layer formation include, for example, silicided source/drain (S/D) regions and silicided gate contact regions. The silicided regions form uniform structures for electrical coupling to underlying doped regions that are parts of one or more semiconductor devices. In integrated circuits in which an etchstop layer is desired for the patterning of the metal film, a first optional insulating layer is deposited prior to deposition of the metal film.

Abstract: A planar motor provides essentially unlimited range of motion in six degrees of freedom to an associated stage, e.g. for photolithography, in either a moving magnet or a moving coil configuration. Moving magnet configurations eliminate cumbersome cables and hoses, and allow higher speed. The motor incorporates checkerboard magnet arrays and/or planar coil arrangements involving overlapped polygonal coil units. Alternatively, the stage is suspended by permanent magnets or by electromagnetic force generated by the motor, allowing the altitude and the tilt angle of the stage to be controlled by commutation of a motor coil. Selective commutation and energizing of coil units conserve power and reduce heat, thermal expansion, and warpage, which otherwise degrade precision. This planar motor provides a single stage to replace conventional stacked stages, thereby increasing effective stiffness and reducing vibration due to low frequency resonances.

Abstract: A touchpad assembly capable of providing an operating surface of a touchpad in a plurality of operating positions. The operating assembly can be adjusted by changing the orientation of the operating surface of the touchpad or by changing the form of the operating surface. The touchpad assembly including a supporting device for supporting the operating surface.

Abstract: Antifuses and gate arrays with antifuses are disclosed that have high thermal stability, reduced size, reduced leakage current, reduced capacitance in the unprogrammed state, improved manufacturing yield, and more controllable electrical characteristics. Some antifuses include spacers in the antifuse via. In some antifuses, the programmable material is planar, and the top or the bottom electrode is formed in the antifuse via. In some gate arrays, the antifuses are formed above the dielectric separating two levels of routing channels rather than below that dielectric.

Abstract: A validity circuit is used with an analog circuit in a mixed signal system to determine whether the supply voltage is at an adequate voltage level to assure stable operation of the analog circuit. The validity circuit generates a "valid" signal that is used to activate the mixed signal system when the voltage level of the supply voltage is adequate. Where the voltage level of the supply voltage is inadequate to produce a stable output signal from the analog circuit, the analog circuit will stop generating a valid signal indicating that any output signal generated by the analog signal is unstable. The logic circuit is thus deactivated to avoid producing inaccurate or unreliable results. Where the analog circuit is a bandgap voltage reference circuit, the validity circuit is connected to two nodes within the feedback loop of the bandgap voltage reference circuit.

Abstract: A mounting bracket for an electronics rack having a rack structure defining a plurality of holes spaced along the rack structure to define retma (U) mounting unit increments of the rack. The plurality of holes are spaced along the vertical rack structure in a pattern substantially conforming to an Electronics Industry Association (EIA) standard. The mounting bracket includes a mounting bracket body, a first alignment structure extending from the mounting bracket body, and a second alignment structure extending from the mounting bracket body. The first alignment structure and the second alignment structure each are adapted to engage a hole of the rack structure so as to align the bracket in a position along the rack structure. The first alignment structure and the second alignment structure being spaced apart such that the bracket is alignable along the rack structure both at positions corresponding to whole retma unit increments and at positions corresponding to half retma unit increments.

Abstract: A method and structure for customizing or repairing integrated circuits using passivated tungsten fuses and low-power energy beams to select which tungsten fuses are to be removed. The tungsten fuses are formed in an array to connect possible connection points of the device. A low-power energy source then selects undesired connection points, and a conventional etch removes the selected tungsten fuses, thereby customizing or repairing the integrated circuit. Because neither precision custom masks nor high energy laser sources are required, the problems associated with conventional methods are reduced or eliminated.

Abstract: A method of making an IGFET and a protected resistor includes providing a semiconductor substrate with an active region and a resistor region, forming a gate over the active region, forming a diffused resistor in the resistor region, forming an insulating layer over the gate and the diffused resistor, forming a masking layer over the insulating layer that covers the resistor region and includes an opening above the active region, applying an etch using the masking layer as an etch mask so that unetched portions of the insulating layer over the active region form spacers in close proximity to opposing sidewalls of the gate and an unetched portion of the insulating layer over the resistor region forms a resistor-protect insulator, and forming a source and a drain in the active region. In this manner, a single insulating layer provides both sidewall spacers for the gate and a resistor-protect insulator for the diffused resistor.

Abstract: Architectural support for generation isolation is provided through trapping of intergenerational pointer stores. Identification of pointer stores as intergenerational is performed by a store barrier responsive to an intergenerational pointer store trap matrix that is programmably encoded with store target object and store pointer data generation pairs to be trapped. The write barrier and intergenerational pointer store trap matrix provide a programmably-flexible definition of generation pairs to be trapped, affording a garbage collector implementer with support for a wide variety of generational garbage collection methods, including remembered set-based methods, card-marking type methods, write barrier based copying collector methods, etc., as well as combinations thereof and combinations including train algorithm type methods to managing mature portions of a generationally collected memory space.

Abstract: A trench power MOSFET includes a body region which is not shorted to the source region and which is entirely covered by the source region within each cell of the MOSFET. The body region within each MOSFET cell is brought to the surface of the substrate (or epitaxial layer overlying the substrate) in an area outside of the MOSFET cell, and is connected to a body contact bus which is electrically insulated from the source bus. A deep diffusion of the same conductivity type as the body region may be formed adjacent the trench gate but outside of a MOSFET cell to protect the gate oxide from excessive field potentials at the corners of the gate. The deep diffusion is also connected to the body contact bus, which may include a metal layer, a submerged region of the second conductivity, or both.