Abstract: A method of making an IGFET with a selected threshold voltage is disclosed. The method includes providing a semiconductor substrate with a device region that includes a source region, a drain region and a channel region therebetween, forming a gate over the channel region, introducing a threshold adjust dopant into the channel region after forming the gate without transferring essentially any of the threshold adjust dopant through the gate, thereby adjusting a threshold voltage of the IGFET, and forming a source in the source region and a drain in the drain region. Preferably, the threshold adjust dopant is introduced by implanting the threshold adjust dopant into the source region and diffusing the threshold adjust dopant from the source region into the channel region before providing any source/drain doping.

Abstract: A serial storage architecture (SSA) storage subsystem which includes an SSA initiator and a series of SSA targets which include disk drives housed in a storage pod and an intelligent backplane of the storage pod which houses the other SSA targets. The intelligent backplane includes a controller, a series of status registers, each indicating status of an operating parameter for the SSA target drives, and a series of control registers, each configured to transmit a respective command to selected ones of said SSA target drives. The controller polls each of the status registers and, based on the contents thereof, determines whether an event relating to the operating parameter has occurred. If so, the controller reports the event to the SSA initiator. The SSA initiator may also control the target drives using the control registers.

Abstract: A velocity-controlled actuator system and method are usable in low velocity, high load situations such as those encountered in dynamic head loading, and in normal situations. The velocity-controlled actuator system utilizes a self-tuning estimator that is calibrated during operation of said disk drive. Consequently, parameters, characteristics, and any other features of the disk drive that affect operation of the actuator system are compensated for in real time by the calibration process. The velocity-controlled actuator system dynamically adjusts the actuator resistance utilized in the reconstruction of the back EMF voltage by utilizing a self-tuning estimate of the actuator resistance that compensates for any changes in the actuator resistance over time.

Abstract: A random access memory (RAM) device includes a buffer in the memory cell to isolate the latching circuit from the read bit line. Consequently, read disturb errors caused by capacitive loading on the read bit line are avoided. Further, the precharge requirements on the write bit line are simplified because the buffer permits optimization of the latching circuit in the memory cell. The RAM device includes a precharge circuit that precharges the write bit line to a ground reference voltage prior to performing write operations. By precharging the write bit line to ground reference voltage, write disturb problems caused by capacitive loading on the write bit line are avoided. Further, by coupling the write bit line to ground reference voltage, little or no power is consumed by precharging the write bit line.

Abstract: A nonperiodic waveform is forced to a periodic character to facilitate looping of the waveform without introducing audible, and thus objectionable, sound artifacts. Nonperiodic waveforms are typically nonperiodic due to the presence of nonharmonic high frequency spectral components. In time, the high frequency components decay faster than low frequency components and looping of the waveform is facilitated. A loop forcing process and loop forcing filter facilitate looping of a nonperiodic waveform by accelerating the removal of the nonperiodic high frequency components. A loop forcing filter accelerates the removal of nonperiodic high frequency components using a comb filter having a frequency selectivity that varies in time.

Abstract: A method for forming a critical dimension test mark, and the use of the mark to characterize and monitor imaging performance is provided. Methods in accordance with the present invention encompass an exposure of an essentially standard critical dimension bar at each of two overlapping orientations that are rotated about an axis with respect to each other. The overlapped portion forming a critical dimension test mark that is useful for enabling low cost, rapid determination of sub-micron critical dimensions for characterizing exposure tool imaging performance and in-process performance monitoring using optical measurement systems.

Abstract: The degradation of integrity of the gate oxide in a CMOS transistor due to the formation of a tungsten silicide strapping layer on the polycrystalline silicon gate as a result of the migration of fluorine atoms from the tungsten hexafluoride used to form the tungsten silicide is reduced by increasing the dopant concentration of the polycrystalline silicon layer thereby to form dopant atoms in the grain boundaries of the polycrystalline silicon to block the migration of fluorine through the polycrystalline silicon to the underlying gate oxide. By preventing fluorine from reaching the gate oxide in this manner, the degradation of the gate oxide due to the replacement of oxygen by fluorine is decreased.

Abstract: A system management mode (SMM) of operating a processor includes only a basic set of hardwired hooks or mechanisms in the processor for supporting SMM. Most of SMM functionality, such as the processing actions performed when entering and exiting SMM, is "soft" and freely defined. A system management interrupt (SMI) pin is connected to the processor so that a signal on the SMI pin causes the processor to enter SMM mode. SMM is completely transparent to all other processor operating software. SMM handler code and data is stored in memory that is protected and hidden from normal software access.

Abstract: An electroless plating apparatus heats a plating bath solution with precise uniformity and avoids localized high temperatures within the bath. The electroless plating apparatus achieves this performance using two solution tanks included an inner tank nested inside an outer tank. A distributed heating element encases a plurality of surfaces of the outer tank, which contains an ethylene glycol solution. The inner tank contains a plating bath solution. A substrate is placed inside the inner tank for plating. Each of the outer tank and the inner tank include a device for evenly distributing the applied heat. In one embodiment, the outer tank heat distributing device is a pump which mixes the ethylene glycol solution. The inner tank heat distributing device is a pump which recirculates plating bath solution, applying returning solution via a sparger.

Abstract: A multi-bit-per-cell memory includes a memory array having reference cells and storage cells, a read circuit, a content addressable memory, and an encoder. When data is written to the memory, a set of reference values for the write are written to the reference cells. The reference values correspond to the multi-bit digital values that can be stored in a single storage cell. For a read operation, the read circuit reads the reference values from the reference cells and stores the reference values in the content addressable memory. The read circuit then reads a data value from a storage cell associated with the reference values and applies the value read to the content addressable memory for a match operation. The output data is equal to the number or address of the entry containing the reference value that matches the data value.

Abstract: The pin count of a processor is substantially reduced while effectively maintaining processor performance by using a staging register to receive and store a first data segment from a bus. A second data segment is received from the bus in a subsequent bus cycle and loaded into a cache. A steering circuit dynamically selects the transfer of the first or the second segment to a processor core, and orders positioning of the first and second data segments into the cache. In some embodiments, the cache is a first level cache and a second level cache is inserted between the bus and the processor. In these embodiments, the processor includes a bypassing circuit for designating the ordering of bus data in response to a memory access that misses the first level cache and hits the second level cache.

Abstract: A decoding process for a MPEG1 audio subband uses the symmetry of filter coefficients to reduce the number of multiplications required to decode an audio subband. The decoding process can be efficiently implemented on a single-instruction-multiple-data (SIMD) processor having vector registers capable of holding multiple samples from the subband. In a particular embodiment, some of samples are stored in a first vector register in a normal order and other samples are stored in a second vector register in a reverse order. For example, for eight data element vector registers, the first vector register contains a series of samples index values 0 to 7, and the second vector register contains a series of samples index values 31 to 24. Such ordering facilitates SIMD instructions which perform parallel operations combining value of index i with values of index 31-i.

Abstract: A thin silicon epitaxial layer, formed on a silicon substrate, is subdivided into electrically isolated pockets by a grid of oxidized regions of epitaxial silicon material which extend through the epitaxial layer to a laterally extending PN junction.

Abstract: A memory system includes a memory, an input circuit and a logic circuit. The input circuit is coupled to receive a memory address and, during a write operation, the corresponding write data to be written into the SRAM. The logic circuit causes the write data to be stored in the input circuit for the duration of any sequential read operations immediately following the write operation and then to be read into the memory during subsequent write operation. During the read operation, data which is stored in the write data is storage registers prior to being read into the memory can be read out from the memory system should the address of one or more read operations equal the address of the data to be written into the memory while temporarily stored in the write data storage registers. Thus, no "bus turnaround" down time is experienced by the system thereby increasing the bandwidth of the system. The system can operate in a single pipeline mode or a dual pipeline mode.

Abstract: A DI fault current leakage guard switching device for detecting improperly wired networks or missing connections includes a totalizing current transformer for detecting fault currents in a phase conductor line and a neutral conductor line, a switching stage, a DI guard switch, and a detecting unit for detecting fault conditions of a protective earth conductor line. The detecting unit receives signals on the phase conductor line, neutral conductor line and protective earth conductor line, respectively. The detecting unit is connected to the switching stage for controlling the DI guard switch.

Abstract: A package for a device includes a substrate having a common voltage plane and a mounting region. The device is mounted to the mounting region. An electrically conductive dam structure is disposed on the upper surface of the substrate circumscribing the perimeter of the mounting region. The electrically conductive dam structure is coupled to the common voltage plane. An electrically insulating encapsulant at least partially fills the pocket defined by the substrate and the electrically conductive dam structure. The electrically insulating encapsulant contacts the electrically conductive dam structure. An electrically conductive encapsulant overlies the electrically insulating encapsulant and is coupled to the electrically conductive dam structure.

Abstract: A method for manufacturing a capacitor, applied to a memory unit including a substrate forming thereon a dielectric layer forming thereon a first conducting layer, includes the steps of a) forming a sacrificial layer over the first conducting layer, b) partially removing the sacrificial layer, the first conducting layer, and the dielectric layer to form a contact window, c) forming a second conducting layer over the sacrificial layer and in the contact window, d) partially removing the second conducting layer and the sacrificial layer to expose a portion of the sacrificial layer and retain a portion of the second conducting layer, and e) forming a third conducting layer alongside the portions of the second conducting layer and the sacrificial layer, and removing the portion of the sacrificial layer to expose the first conducting layer, wherein the first conducting layer, the portion of the second conducting layer, and the third conducting layer construct a capacitor plate with a generally crosssectionally mod

Abstract: In the present method, a semiconductor substrate is provided with an epitaxial layer thereon. A source/drain region is provided in a portion of the epitaxial layer, and a plurality of trenches are etched in the epitaxial layer and extend into the substrate, to define a plurality of mesas.An oxide layer of generally uniform thickness is provided over the mesas and in the trenches, and a polysilicon layer is provided over the oxide layer and is etched so that the oxide layer overlying the mesas is exposed, and the top surface of the polysilicon within the trenches is below the level of the tops of the mesas.A layer of spin-on-glass (SOG) is provided, and the SOG layer and oxide layer are etched substantially to the level of the tops of the mesas, to expose the tops of the mesas and to leave the portions of the SOG over the respective polysilicon portions in the trenches substantially coplaner with the tops of the mesas.

Abstract: A high voltage MOS device includes a P-type substrate having an N-type buried layer formed therein. An N-type epitaxial layer overlies the substrate and a P-type well is formed in the epitaxial layer. A source region is formed in the well such that the source region is directly in contact with the well. No intermediate layer is disposed between the source region and the well. A drain region includes an extended drain region. The extended drain region, which is formed within and in contact with the well, comprises different dopant species and has a maximum dopant concentration of 3.5.times.10.sup.17 cm.sup.-3. A heavily doped main drain region is formed within and in contact with the extended drain region. The source region and extended drain region define a channel region therebetween in the well. An insulator is on a surface of the well over the channel region. A gate is over the insulator.

Abstract: A DI fault current leakage guard switching device for detecting improperly wired networks or missing connections includes a totalizing current transformer for detecting fault currents in a phase conductor line and a neutral conductor line, a switching stage, a DI guard switch, and a detecting unit for detecting fault conditions of a protective earth conductor line. The detecting unit receiving signals on the phase conductor line, neutral conductor line and protective earth conductor line, respectively. The detecting unit is connected to the switching stage for controlling the DI guard switch.