Patents Represented by Attorney, Agent or Law Firm Skjerven Morrill MacPherson Franklin & Friel
  • Patent number: 6086175
    Abstract: An altar includes a cabinet body and a platform, which is located in front of the cabinet body and which has a flat top surface. The cabinet body has an interior chamber and several columns of compartments, each of which is open to the interior chamber and each of which is provided with an openable door. Several box sets are disposed within the interior chamber, and are located respectively behind the columns. Each of the box sets includes an endless flexible member which can be circulated by a driving unit, and a plurality of boxes which are attached to the flexible member. Each of the flexible members can be controlled by a switch member to circulate or stop. Accordingly, each of the boxes can be moved to be aligned with a selected corresponding column of the compartments.
    Type: Grant
    Filed: November 12, 1998
    Date of Patent: July 11, 2000
    Inventor: Chun-Tse Yang
  • Patent number: 6087706
    Abstract: A semiconductor integrated circuit with a transistor formed within an active area defined by side-walls of a shallow trench isolation region, and method of fabrication thereof, is described. A gate electrode is formed over a portion of the active area and LDD regions formed that are self-aligned to both the gate electrode and the trench side-walls. A dielectric spacer is formed adjacent the gate electrode and extending to the trench side-walls. In this manner, the spacers essentially cover the LDD regions. Source and drain regions are formed that are adjacent the trench side-walls wherein the spacer serves to protect at least a portion of the LDD regions to maintain a spacing of the S/D regions from the gate electrode edge. In this manner an advantageously lowered E.sub.M provided by LDD regions is maintained. In some embodiments of the present invention, S/D regions are formed by implantation through the trench side-walls.
    Type: Grant
    Filed: April 7, 1998
    Date of Patent: July 11, 2000
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Robert Dawson, Mark I. Gardner, Frederick N. Hause, H. Jim Fulford, Jr., Mark W. Michael, Bradley T. Moore, Derick J. Wristers
  • Patent number: 6087722
    Abstract: A multi-chip stack package does not include a die pad. The elimination of the die pad provides more room for elements in the package which. Thus, a balanced inner package structure can be achieved, and a poor molding which may expose one of the package elements can be avoided. In the package, an upper chip is bonded to the top surface of a lower chip. To stabilize the chips, auxiliary or inner leads of a lead frame attach to the top surface of a lower chip. This shortens wire lengths between the chips and the inner leads. The shorter wires reduce wire loop heights and thus reduce the probability of exposing wires in a subsequent transfer-molding. A multi-chip stack package which includes an auxiliary lead(s) is also disclosed. The auxiliary leads attach to the top surface of the lower chip and can provide a stable support of a semiconductor chip and prevent the chip from tilting and shifting in transfer-molding. An auxiliary lead can be between the lower and upper chips.
    Type: Grant
    Filed: April 14, 1999
    Date of Patent: July 11, 2000
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kwan Jai Lee, Young Jae Song, Do Soo Jeong, Tae Je Cho, Suk Hong Chang, Chang Cheol Lee, Beung Seuck Song, Jong Hee Choi
  • Patent number: 6087200
    Abstract: A process for packaging a die uses compressible microspheres to form a stress buffer layer between the die and an epoxy encapsulant to absorb stresses on the die caused by the different thermal expansion rates of the epoxy and die during temperature changes. By using a compressible layer of microspheres or other material, the need for a nitride passivation or other insulating layer to protect the die from thermally-induced stress is eliminated. In addition, the number and size of the microspheres and the amount of epoxy used to seal the package can be adjusted so that the epoxy is approximately co-planar with the top of the package to allow the package to be handled and used with standard equipment and processes.
    Type: Grant
    Filed: August 13, 1998
    Date of Patent: July 11, 2000
    Assignee: Clear Logic, Inc.
    Inventor: John MacPherson
  • Patent number: 6086003
    Abstract: The invention relates to a roll press, in particular for processing very abrasive materials, comprising at least two press rolls of which each includes a wear layer arranged on a basic body. The wear layer comprises substantially plane zones of a highly wear-resistant material while the spaces between the highly wear-resistant zones are filled with a material of different wear resistance. Furthermore, the material for the spaces is a composite material which is adapted to be sintered, and the highly wear-resistant zones are formed from hard bodies produced by hot-isostatic pressing. The material for the spaces and the material for the wear-resistant zones are bonded to the basic body in a hot-isostatic pressing process. The wear resistance of the composite material is substantially slightly greater or smaller than the wear resistance of the hard bodies in accordance with a desired profile which will obtained through wear.
    Type: Grant
    Filed: May 26, 1998
    Date of Patent: July 11, 2000
    Assignee: Maschinenfabrik Koppern GmbH & Co. KG
    Inventors: Harald Gunter, Werner Plagemann, Wolfgang Schutze
  • Patent number: 6086456
    Abstract: A polishing system such as a chemical mechanical belt polisher includes a hydrostatic fluid bearing that supports polishing pads and incorporates one or more of the following novel aspects. One aspect uses compliant surfaces surrounding fluid inlets in an array of inlets to extend areas of elevated support pressure around the inlets. Another aspect modulates or reverses fluid flow in the bearing to reduce deviations in the time averaged support pressure and to induce vibrations in the polishing pads to improve polishing performance. Another aspect provides a hydrostatic bearing with a cavity having a lateral extent greater than that of an object being polished. The depth and bottom contour of cavity can be adjusted to provide nearly uniform support pressure across an area that is surrounded by a retaining ring support. Changing fluid pressure to the retaining ring support adjusts the fluid film thickness of the bearing.
    Type: Grant
    Filed: November 6, 1998
    Date of Patent: July 11, 2000
    Assignee: Aplex, Inc.
    Inventors: David E. Weldon, Shu-Hsin Kao, Tim H. Huynh
  • Patent number: 6087269
    Abstract: An interconnect layer is fabricated using a tungsten hard mask by forming a tungsten based layer over an aluminum based layer. A photoresist layer is deposited over the tungsten based layer and patterned. The tungsten based layer is patterned by applying a fluorine-based etchant using the photoresist layer as an etch mask. Then the aluminum based layer is patterned by applying a chlorine based etchant using the tungsten based layer as an etch mask.
    Type: Grant
    Filed: April 20, 1998
    Date of Patent: July 11, 2000
    Assignee: Advanced Micro Devices, Inc.
    Inventor: John David Williams
  • Patent number: 6087854
    Abstract: An improved line driver is disclosed. In one embodiment, the line driver has three inverters and a pass gate. The first inverter has a first input terminal connected directly to the input line of the line driver. The first inverter also has an output terminal coupled to a first output line of the line driver. The second inverter has an output node coupled to a second output line of the line driver. The third inverter has a first input terminal connected directly to the input line of the line driver and an output terminal coupled to the input node of the second inverter. The pass gate has a second input terminal coupled to the input line of the line driver and an output terminal coupled to both the second input terminal of the first inverter and the second input terminal of the third inverter. The pass gate receives an enable signal at a first input terminal and provides a conduction path between the input line of the line driver and the output terminal of the pass gate in response to the enable signal.
    Type: Grant
    Filed: September 2, 1998
    Date of Patent: July 11, 2000
    Assignee: Lattice Semiconductor Corporation
    Inventor: Dale A. Potter
  • Patent number: 6084452
    Abstract: An apparatus adjusts the duty cycle of a single-ended clock signal. The single-ended clock signal oscillates between first and second voltages. The apparatus includes an error indication circuit, a duty cycle error measurement circuit and a duty cycle adjuster. The error indication circuit includes a reference circuit and a comparison circuit. The reference circuit is coupled to a first node having the first voltage and a second node having the second voltage to generate a reference signal from the first and second voltages. The reference circuit includes at least one instance of a first electrical characteristic cell. The comparison circuit is coupled to receive a feedback clock signal and to generate a comparison signal therefrom. The comparison circuit includes at least one instance of the first electrical characteristic cell. The duty cycle error measurement circuit is coupled to receive the reference signal and the comparison signal.
    Type: Grant
    Filed: June 30, 1998
    Date of Patent: July 4, 2000
    Assignee: Sun Microsystems, Inc
    Inventors: Robert J. Drost, Jose M. Cruz, Robert J. Bosnyak
  • Patent number: 6084428
    Abstract: A field programmable gate array has columns of logic modules. A programming conductor used to conduct programming current to program antifuses of the field programmable gate array extends between two adjacent columns of logic modules. First wire segments extend from the programming conductor and toward the logic modules of a first of the two adjacent columns. Second wire segments extend the opposite direction from the programming conductor and toward logic modules of the second of the two adjacent columns. Programming current used to program antifuses disposed along the first wire segments as well as antifuses disposed along the second wire segments can be supplied from the same programming conductor that extends between the two columns of logic modules. The logic modules of the first column are mirrored versions of the logic modules of the second column.
    Type: Grant
    Filed: September 17, 1997
    Date of Patent: July 4, 2000
    Assignee: QuickLogic Corporation
    Inventors: Paige A. Kolze, James A. Apland
  • Patent number: 6084706
    Abstract: A laser scanner includes an optical relay which reforms an image from a scan lens at a location that provides additional working distance. The optical relay contains primarily reflective elements which provide achromatic focusing for ultraviolet light. One embodiment of the optical relay has a magnifying power of about 1 and use spherical mirrors in a configuration where image distortion and aberrations cancels. A second optical relay provides a reduction in image size using aspherical mirrors such as parabolic and elliptical mirrors. An additional lens cancels distortion and aberration introduced in the second optical relay. The additional working distance allows insertion optical devices such as beamsplitters and chevron correction and autofocus optics in the optical path of the optical relay.
    Type: Grant
    Filed: May 20, 1998
    Date of Patent: July 4, 2000
    Assignee: Etec Systems, Inc.
    Inventors: John M. Tamkin, Joseph P. Donahue
  • Patent number: 6084454
    Abstract: Some logic circuits preferentially reside in a particular state. Advantages are gained by a circuit that forces the circuit to the preferential state but allows the preferred state to be overridden. A node in the logic circuit is driven to a particular state, in one embodiment, by a pull-up transistor connected to a pull-down transistor that respectively drive the node to a high state and a low state. A keeper circuit is connected to the node and drives the node to the preferred state unless overpowered by the pull-up transistor and the pull-down transistor. The keeper circuit drives the node using a transistor that is weaker than the pull-up transistor and weaker than the pull-down transistor. A startup-circuit is connected to the node and drives the node to the preferred state when the node powers-up in the nonpreferred state. The start-up circuit drives the node using a transistor that is weaker than the keeper circuit transistor.
    Type: Grant
    Filed: August 26, 1998
    Date of Patent: July 4, 2000
    Assignee: Advanced Micro Devices, Inc.
    Inventor: John C. Holst
  • Patent number: 6084469
    Abstract: A circuit and method for lowering the corner frequency of a differential preamplifier having an AC coupling circuit includes a compensation circuit to adjust the frequency response characteristics created by the AC coupling circuit. An RC network in the compensation circuit is configured to provide a canceling zero at the corner frequency of the AC coupling circuit. The RC network also provides a pole at a desired frequency lower than the corner frequency of the AC coupling circuit, in order to define the overall preamplifier corner frequency. The compensation circuit allows the capacitance in the AC coupling circuit to be significantly reduced, eliminating the need for external components or a very large integrated capacitance.
    Type: Grant
    Filed: March 20, 1998
    Date of Patent: July 4, 2000
    Assignee: National Semiconductor Corporation
    Inventor: Perry Lorenz
  • Patent number: 6085033
    Abstract: A method for determining bit element values for an impedance control circuit is provided which controls the output impedance of drivers which are coupled to the impedance control circuit. Accordingly, a desired driver output impedance can advantageously be established and maintained over a wide range of variations in operating conditions and manufacturing processes. Thereby shortening the signal settling time and increasing the attainable signaling frequency.
    Type: Grant
    Filed: June 25, 1997
    Date of Patent: July 4, 2000
    Assignee: Sun Microsystems, Inc.
    Inventors: Jonathan E. Starr, Sai V. Vishwanthaiah, Alexander D. Taylor
  • Patent number: 6082377
    Abstract: A wafer cleaning and drying apparatus comprises a vertical wafer drive assembly providing two-sided wafer cleaning by symmetrically disposed brushes. Each wafer brush comprises two parallel rotatable shafts within the lumen of a substantially tubular sponge, with an adjustable distance between the two shafts, which is narrowed to facilitate insertion into the sponge and widened to stretch the sponge into a substantially oval cross-sectional shape, thereby improving traction. One or more nonrotating perforated fluid delivery tubes are mounted within the lumen of the sponge in the space between the two shafts. The apparatus further comprises a minimal volume rinse/dry enclosure that conserves water and process chemicals; and a wafer transport assembly configured to transfer multiple wafers simultaneously between multiple process stations.
    Type: Grant
    Filed: May 21, 1999
    Date of Patent: July 4, 2000
    Inventor: Bernhard M. Frey
  • Patent number: 6082636
    Abstract: In a washer nozzle assembly, the upper lip portion defining a nozzle opening extends more forwardly than the lower lip portion so that the part of the washer liquid directed upward is blocked by the longer upper lip portion, and the upper part of the spray pattern includes more liquid droplets of larger sizes as compared to the prior art. Thus, the loss of washer liquid by being flown above the windshield at high speed can be reduced, and the spray pattern of the washer nozzle assembly can be optimized for all speeds.
    Type: Grant
    Filed: August 5, 1999
    Date of Patent: July 4, 2000
    Assignees: Honda Giken Kogyo Kabushiki Kaisha, Mitsuba Corporation
    Inventors: Yasuhiko Yoshida, Akira Takayama, Koji Iwazaki, Takatoshi Kondo
  • Patent number: 6084770
    Abstract: A heat sink mounted on an electronic component causes a thermal plume effect so that air adjacent to the electronic component moves through one or more channels in the heat sink in a direction substantially transverse to and away from the electronic component. The heat sink includes a base attachable to the electronic component, a support member mounted on and substantially transverse to the base, and a heat exchanger mounted on the support member and spaced away from the base. The heat exchanger has at least one entry hole adjacent to the base, at least one exit hole at a distance from the entry hole, and one or more channels adjacent to the support member and in flow communication with the entry hole and the exit hole.
    Type: Grant
    Filed: July 9, 1997
    Date of Patent: July 4, 2000
    Assignee: Integrated Device Technology, Inc.
    Inventor: Christopher P. Wyland
  • Patent number: 6084525
    Abstract: The distress call emitting device comprises an earthquake sensor for detecting an earthquake of a prescribed intensity or greater and/or a receiver for receiving a radio signal from a remote transmitter. Therefore, even when the user is unable to call for a help, the distress call emitting device of the present invention produces a distress call in his behalf by sound and/or light. The distress call can be initiated either by detecting the intensity of the earthquake or by operating a remote transmitter which may be carried by the user. If the device is linked to a telephone line, the distress call can be made also through a telephone line. Thus, even when the user is too weak to call for a help by his own effort, the device is either automatically activated by an earthquake or remotely activated by pressing a switch on a portable transmitter.
    Type: Grant
    Filed: May 14, 1998
    Date of Patent: July 4, 2000
    Assignee: Kabushiki Kaisha Alpha Tsushin
    Inventors: Katsunori Toyota, Nobuo Kimura, Masayuki Kaga
  • Patent number: 6084284
    Abstract: A method of semiconductor fabrication includes the steps of forming a dielectric layer on a first surface of a semiconductor wafer having a plurality of laterally distributed semiconductor devices selectively interconnected on the first surface and bonding a support substrate to the first surface of the semiconductor wafer on the dielectric layer to form a composite structure. A portion of the semiconductor wafer from a second surface which is opposite the first surface is removed and the second surface of the semiconductor wafer is processed. Processing of the second surface optionally includes the formation of isolation trenches electrically isolating the laterally distributed semiconductor devices.
    Type: Grant
    Filed: October 26, 1999
    Date of Patent: July 4, 2000
    Inventor: Fred W. Adamic, Jr.
  • Patent number: D427446
    Type: Grant
    Filed: November 13, 1997
    Date of Patent: July 4, 2000
    Assignee: Shin Yen Enterprise Co., Ltd.
    Inventor: Chuen-Jong Tseng