Abstract: In a video conferencing system, a video overlay system (160) generates a motion video signal (MV). The motion video signal incorporates an image received from a remote video conferencing system (110.2) and from a local camera (186). The video overlay system also receives a computer video signal (CV) from a local computer (140). A summing amplifier (310) in the video overlay system generates an output signal (SV) representative of the sum of the computer video signal and the motion video signal. The output signal (SV) is provided to a monitor (174) when motion video is to be displayed. Use of the summing amplifier allows a cursor (240) generated by the computer to be inserted into the motion video on the monitor screen.

Abstract: A method of operation of a computer system for processing an arbitrary document such as a World Wide Web page to provide additional information not immediately available from the raw, unprocessed document. This additional information allows a user to navigate and control the content of the document using, in some embodiments, voice commands and/or an agent-based user interface. The present disclosure provides both a visual display of previously invisible links embedded in a web page image and an audible indication of the presence of such links. The present invention further comprises a scripting language that allows the rapid creation of executable computer instructions (or scripts) for controlling the behaviors and functionality of the agent-based interface. Such scripts enable the creation of a friendlier, easy to use interface to the navigation and control features.

Abstract: A system for uniformly and controllably heating the active surface of a semiconductor wafer or substrate during processing. The present invention may include a radiation energy source provided, which is enclosed or substantially surrounded by a reflective/absorptive surface, which both reflects and absorbs the radiation, emitted from the energy source. In accordance with the present invention, the resultant energy output as seen by the wafer is substantially free of non-uniformity.

Abstract: An analog-to-digital converter is disclosed, including: a reference generator circuit for generating a plurality of reference voltages; a plurality of amplifying comparators for receiving the reference voltages and analog input signals, each amplifying comparator including: two amplifying paths, each of which has a first amplifier and a second amplifier for alternatively receiving signals from the two paths; a latching comparator having a plurality of latches and receiving output signals from the amplifying comparator; and a digital decoder receiving output signals from the latching comparator and generating a predetermined number of data bits.

Abstract: The present invention provides a shared instruction cache for multiple processors. In one embodiment, an apparatus for a microprocessor includes a shared instruction cache for a first processor and a second processor, and a first register index base for the first processor and a second register index base for the second processor. The apparatus also includes a first memory address base for the first processor and a second memory address base for the second processor. This embodiment allows for segmentation of register files and main memory based on which processor is executing a particular instruction (e.g., an instruction that involves a register access and a memory access).

Abstract: An MPEG video decoder adapted to decode an incoming MPEG coded video data stream to form decoded MPEG video data and to reconstruct from the decoded MPEG video data a raw video signal, utilizes: an n×n block of decoded video data discrete cosine transform values forming an original matrix having a non-zero value in a preselected corner location in the matrix; and a modified matrix forming apparatus adapted to form a modified matrix having the same content as the original matrix with the exception of a zero in the preselected corner value position; a dummy matrix forming apparatus adapted to form a dummy matrix having zero in each of its matrix positions with the exception of the preselected corner position; an inverse discrete cosine transform apparatus adapted to perform an inverse discrete cosine transform algorithm on the modified matrix and the dummy matrix; and an adder which adds the inverse discrete cosine transform of the modified matrix and the dummy matrix to produce the inverse discrete cosin

Abstract: A semiconductor package manufacturing method includes: providing a rerouting film; attaching a semiconductor wafer having integrated circuits to the rerouting film, such that chip pads of the integrated circuits correspond to via holes of the rerouting film; forming a solder filling in each of the via holes to electrically connect the chip pads to the metal pattern layer; forming external terminals on terminal pads of the rerouting film; and separating the wafer and the rerouting film into individual semiconductor packages. A method further includes forming a protection layer on the solder filling. Instead of the semiconductor wafer, individual integrated circuit chips can be attached on the rerouting film.

Abstract: A projection exposure apparatus for exposing a semiconductor wafer to a pattern, formed on a reticle, using a projection lens system. An alignment optical system is disposed at a backside of the wafer which is remote from the projection lens system. The alignment optical system detects an alignment mark provided on the frontside of the wafer from the backside of the wafer. Thus the wafer alignment mark is detected without being adversely affected by integrated circuit layers, e.g. photoresist, metallization, etc. applied to the principal surface (frontside) of the wafer, and the reticle and wafer can be aligned accurately. Any tilting or wedging of the wafer, i.e. non-normality to the incident light beam, is detected and corrected for.

Abstract: A wafer processing system employing a single-wafer load lock with a cooling unit is disclosed. The small volume of the single-wafer load lock allows for fast pump down and vent cycles. By providing a cooling unit within the load lock, system throughput is further increased by eliminating the need to move a newly processed wafer to a separate cooling station before moving the wafer to the load lock. In another embodiment, the wafer processing system includes a load lock having the capability to both heat and cool a wafer. This further increases throughput in processes where the wafer needs to be pre-heated before putting the wafer in the reactor by eliminating the need for an intermediate pre-heating station.

Abstract: A multi-part shielding system obstructs an energy source opening within a connector housing when no connector is present within the housing. The shield is at least as wide as the energy source opening and is configured to rest in a position, when no connector is present in the housing, that obstructs the laser source opening. When a connector is inserted into the connector housing, the connector supplies an obstruction force to the shielding device, causing the shielding device to remain in a deflected position. When the connector is removed from the connector housing, and the obstruction force is therefore removed from the shielding device, and the bias portion of the shielding device causes the device to return to a rest position that again obstructs the energy source opening. The bias portion receives support from a bias support member.

Abstract: A single chip superheterodyne AM receiver is disclosed herein. The receiver has a control pin for application of control signals to adjust a frequency response of a baseband filter to tailor its frequency response to a particular type of signal received by the receiver. Various techniques are described for enabling a complete superheterodyne AM receiver to be implemented on a single chip which receives an antenna input signal and outputs a digital data signal.

Abstract: A method and system for substantially undetectable data processing. The method and system provide data processing systems with an ability to detect a specific event, and enter a background activity state in response to the specific event detected. The specific event detected can be some type of background activity state initiation event, such as a wake event or a time-out event. The entry of a background state in response to the specific event detected can be the initiation of a background routine appropriate to the specific event, such as the initiation of a routine capable of controlling system temperature by passive means.

Abstract: The invention provides for hardware processing of ACLs and thus hardware enforcement of access control. A sequence of access control specifiers from an ACL are recorded in a CAM, and information from the packet header is used to attempt to match selected source and destination IP addresses or subnets, ports, and protocols, against all the ACL specifiers at once. Successful matches are input to a priority selector, which selects the match with the highest priority (that is, the match that is first in the sequence of access control specifiers). The specified result of the selected match is used to permit or deny access for the packet without need for software processing, preferably at a rate comparable to wirespeed. The CAM includes an ordered sequence of entries, each of which has an array of ternary elements for matching “0”, “1”, or any value, and each of which generates a match signal.

Abstract: A process of manufacturing a trench capacitor having a hill structure includes the steps of providing a semiconductor substrate, forming a passivation layer on the semiconductor substrate, etching the passivation layer to form a trench defined by a side wall and a bottom surface, forming a spacer on the side-wall, wherein the bottom surface includes a first part covered by the spacer and a second part exposed from the spacer, forming a sacrificial layer between the spacer and the second part, and removing the sacrificial layer until the spacer has been fully removed to expose the first part wherein an etched rate of the sacrificial layer is slower than that of the spacer, thereby forming the trench capacitor with the hill structure.

Abstract: A method for dispensing a liquid onto a tape having at least one window. The method involves supplying a tape having at least one window and attaching a film to one side of the tape. Liquid is dispensed to the side of the tape opposite the side to which the film is applied. The film is thereafter separated from the tape.

Abstract: A closed caption decoder includes circuitry for processing closed caption according to the Electronic Industries Association EIA-708 and EIA-608 standards. The EIA-708 memory buffers (48) store caption data both for the EIA-708 and the EIA-608 standards. Therefore, the decoder memory requirements are reduced.

Abstract: The present invention provides software branch prediction filtering for a microprocessor. In one embodiment, a method for a software branch prediction filtering for a microprocessor includes determining whether a branch is “easy” to predict, and predicting the branch using software branch prediction if the branch is easy to predict. Otherwise (i.e., the branch is “hard” to predict), the branch is predicted using hardware branch prediction. Accordingly, more accurate but space-limited hardware branch prediction resources are conserved for hard-to-predict branches.

Abstract: A dual damascene process and structure for fabricating semiconductor devices are disclosed. In one embodiment of the invention, a protection layer is deposited on top of a metal layer to protect the metal layer during subsequent etching of an oxide layer to form the via and damascene trench. Because the selectivity between the oxide layer and the protection layer is high, the number and complexity of processing steps are thereby reduced. Other embodiments of the present invention use a metal sealant layer and/or anti-reflective coating in conjunction with the protection layer in a dual-damascene process.

Abstract: A bandgap voltage reference circuit with no error amplifier circuit includes a chain of complementary emitter follower circuits that are connected to a supply voltage and to common ground via respective current mirrors. Each emitter follower circuit within the chain of emitter follower circuits generates a base to emitter voltage. Because of the successive configuration of the chain of emitter follower circuits, the base to emitter voltage differences from all the emitter follower circuits are summed together. Using a chosen number of emitter follower circuits along with an appropriately chosen area for the emitters of the transistors within the emitter follower circuits, the desired proportional to absolute temperature voltage is generated. Further, because of the additive nature of the base to emitter voltage differences, as opposed to a multiplicative nature as found in conventional circuits, the bandgap voltage reference circuit has a decreased level of noise and process sensitivity.