Abstract: A universal serial bus transceiver is disclosed. In one embodiment, the transceiver includes a differential transmitting amplifier with a first input terminal that receives a reference voltage, a second input terminal that receives a first data input signal at a level corresponding to the reference voltage, and a third input terminal that receives a second data input signal at the reference voltage level. The differential transmitting amplifier generates first and second bus data output signal at the bus signal level in response to the first and second data input signals. The transceiver also includes a first receiving amplifier with a first input terminal that receives the reference voltage and a second input terminal that receives a first bus data input signal at the bus signal level. The first receiving amplifier generates a first data output signal at the reference voltage level.

Abstract: An optical retro-reflective apparatus for application to reconfigurable displays for highway signs and other applications is disclosed. In a first preferred embodiment, the apparatus includes a retro-reflector such as a corner cube prism, three orthogonally arranged planer reflectors, or a plurality of either arranged as an array, or an array of micro-spheres or micro-prisms arranged as a corner-cube. In one embodiment, a holographic diffraction element is placed between a source of radiation such as visible light and one or more of the retro-reflectors. The diffraction element is made up of one or more stacked holographic devices in which pre-determined holographs are stored, operative to diffract a particular wavelength band of radiation (e.g. red, blue and green visible light). The hologram devices can be stacked and selectively deactivated so that the desired wavelength band (or color) to be diffracted is selected.

Abstract: A fan speed control system for controlling the operation and speed of a fan is described. The fan speed control system includes a power control block for supplying an output voltage to the fan. An integrated circuit fan controller causes a resistor divider circuit to operably divide a selected portion of the output voltage. The integrated circuit fan controller comprises a data register which receives values indicative of control or speed operands from a host. A logic state machine translates these values into appropriate logic signals and provides the signals to the resistor divider circuit. A timing reference or an oscillator controls the proper sequencing and timing relationship of the logic state machine. To turn the fan on, the following sequence of steps occurs. The power control block is turned off causing the output voltage not to be supplied to the fan. The logic state machine controls the resistor divider circuit to divide the output voltage to be supplied to the fan.

Abstract: The present invention is directed to a multiport metering pump that can completely deliver a very small volume of liquid. The multiport metering pump includes a number of ports (or valve units), each of which can be used as either an outlet valve or an inlet valve. The multiport metering pump includes: a central gallery; a displacement unit; multiple valve units; and multiple conduits that respectively connect the displacement unit and the valve units to the central gallery. The displacement unit and the valve units communicate with the central gallery, and any of the valve units can be used as an inlet valve or outlet valve for the liquid delivery.

Abstract: A network controller, which allows data frames received to be held in an internal memory buffer, has the capability to selectively switch between a DMA mode of data transfer and a non-DMA mode of data transfer to move data frames from the internal memory buffer to a desired location. When the overflow of the memory buffer is anticipated, a DMA controller is automatically engaged to move the data frames to a system memory to prevent the received frames from being discarded. An auto-DMA decision logic engages the DMA controller based on factors such as the number of data frames accumulated in the memory buffer, remaining capacity of the memory buffer, frame loading and unloading rates, and time interval during which data frames have been received without completely unloading the memory buffer.

Abstract: A highly efficient bit encoder and a method related thereto are provided. The bit encoder transmit DC-balanced digital signals over a transmission line. To provide a DC-balanced signal, an input word's single-word disparity (SWD) value is compared to a running word disparity (RWD) value retrieved from a memory register. The RWD value indicates the cumulative DC-imbalance on the transmission line. If the disparity relationship of the SWD and the RWD satisfy a set of predefined rules, the input word is inverted to thereby offset the RWD. An inversion bit is appended to the digital input word to provide an output digital word to indicate to a receiver whether the transmitted output word is inverted to thereby permit recovery of the original system word. In one application, the DC-balanced signal transmits alternately control words and data words.

Abstract: A heat exchanger is used to transfer heat from water to liquid nitrogen. As heat is transferred from the water to the liquid nitrogen, the temperature of the water becomes lower and the liquid nitrogen converts to gaseous nitrogen. The cooled water and gaseous nitrogen are used by one or more semiconductor fabrication equipment in the semiconductor fabrication process. Thus, overall power consumption of the semiconductor fabrication process is lowered because water is cooled by passing the water by liquid nitrogen to convert the liquid nitrogen to gaseous nitrogen for use in the semiconductor fabrication process.

Abstract: A computation unit computes a division operation Y/X by determining the value of a divisor reciprocal 1/X and multiplying the reciprocal by a numerator Y. The reciprocal 1/X value is determined using a quadratic approximation having a form: Ax2+Bx+C, where coefficients A, B, and C are constants that are stored in a storage or memory such as a read-only memory (ROM). The bit length of the coefficients determines the error in a final result. Storage size is reduced through use of “least mean square error”techniques in the determination of the coefficients that are stored in the coefficient storage. During the generation of partial products x2, Ax2, and Bx, the process of rounding is eliminated, thereby reducing the computational logic to implement the division functionality.

Abstract: A light emitting device and a method of fabricating the device utilize a supplementary fluorescent material that radiates secondary light in the red spectral region of the visible light spectrum to increase the red color component of the composite output light. The secondary light from the supplementary fluorescent material allows the device to produce “white” output light that is well-balanced with respect to color for true color rendering applications. The supplementary fluorescent material is included in a fluorescent layer that is positioned between a die and a lens of the device. The die is preferably a GaN based die that emits light having a peak wavelength of 470 nm. The fluorescent layer also includes a main fluorescent material. Preferably, the main fluorescent material is Cerium (Ce) activated and Gadolinium (Gd) doped Yttrium Aluminum Garnet (YAG) phosphor (“Ce:YAG phosphor”).

Abstract: A spread spectrum modulation technique uses digital control logic to switch back and forth between two feedback divider ratios so that the PLL spreads output clock frequency between two limits determined by the ratios. The spread spectrum control logic can be integrated into any PLL frequency synthesizer.

Abstract: A processor includes a “four-dimensional” register structure in which register file structures are replicated by N for vertical threading in combination with a three-dimensional storage circuit. The multi-dimensional storage is formed by constructing a storage, such as a register file or memory, as a plurality of two-dimensional storage planes.

Abstract: A high voltage transistor exhibiting high gated diode breakdown voltage, low leakage and low body effect is formed while avoiding an excessive number of costly masking steps. Embodiments include providing a high gated diode breakdown voltage by masking the high voltage junctions from the conventional field implant and masking the source/drain regions from the conventional threshold adjust implant. Angled openings are formed in the field implant blocking mask so that the field implant at varying distances away from the junctions, thus achieving low leakage and a high gated diode breakdown voltage. The field implant blocking mask is extended over the channel area, thereby producing a transistor with low body effect.

Abstract: In a microprocessor system, a program counter circuit generates a program counter value that represents a retrieved instruction and that includes a more significant portion, a less significant portion, and a carry signal for use in determining a next program counter value. An execute program counter circuit generates an execute program counter value from the less significant program counter value and from the carry signal. The execute program counter value represents a program counter value of an executed instruction.

Abstract: An automated method and apparatus for classifying a customer service activation request (SAR) according to whether repeatable, schedulable, or scaleable elements are present. When the request has no repeating elements, a traditional SAR is forwarded and serviced by the network management system according to provisions well-known in the art. In the more complex case, however, a SAR comprises elements that are both repeatable and schedulable and is thus classified as a service activation module (SAM). An automated process first determines the starting quality of service (QoS) level at the beginning of the service life cycle requested by the customer. The process next determines the life cycle ending time as well as the trigger times at which elements repeat or are reinitiated. In some embodiments of the present invention, the SAM is examined for resource availability. If one or more resources are not available during the service life cycle, the process generates a report.

Abstract: An integrated circuit device having a first type of pads with a probing portion and a bonding portion. The integrated circuit device includes a memory cell array, a logic circuit, and a plurality of the first type of pads and a plurality of a second type of pads. The second type of pads are electrically connected to the logic circuit. The first type of pads are electrically connected to the memory cell array and the logic circuit. Only the probing portion of the first type of pads is contacted by probes during testing of the memory cell array, and the bonding portion is used exclusively for attachment of a bond wire to permit connection to an external system.

Abstract: A triple-poly process forms a static random access memory (SRAM) which has a compact four-transistor SRAM cell layout. The cell layout divides structures among the three layers of polysilicon to reduce the area required for each cell. Additionally, a contact between a pull-up resistor formed in an upper polysilicon layer forms a “strapping” via which cross-couples a gate region and a drain region underlying the strapping via. Pull-up resistors extend across boundaries of cell areas to increase the length and resistance of the pull-up resistors.

Abstract: A method of computing a square root or a reciprocal square root of a number in a computing device uses a piece-wise quadratic approximation of the number. The square root computation uses the piece-wise quadratic approximation in the form: squareroot(X)={overscore (A)}ix2+{overscore (B)}ix+{overscore (C)}i, in each interval i. The reciprocal square root computation uses the piece-wise quadratic approximation in the form: 1/squareroot(X)=Aix2+Bix+Ci, in each interval i. The coefficients {overscore (A)}i, {overscore (B)}i, and {overscore (C)}i, and Ai, Bi, and Ci are derived for the square root operation and for the reciprocal square root operation to reduce the least mean square error using a least squares approximation of a plurality of equally-spaced points within an interval. In one embodiment, 256 equally-spaced intervals are defined to represent the 23 bits of the mantissa.

Abstract: A digital calibration system for an analog-to-digital converter system includes a computational system receiving digital bits from an analog-to-digital converter representing selection of elements of the digital-to-analog converter in response to an analog input. The computational engine produces a digital output representative of the analog input during conversion operation, and digital values for adjustment of an adjustable analog source during calibration. Further, a digital system comprises a radix-less-than-two non-configurable digital-to-analog converter, a comparator system connected to the converter, and a computational system configured for SAR calibration and conversion.

Abstract: A thermal management of a computer system may be advantageously obtained by predicting temperature variations based upon past temperature readings. Such a system may, in preferred embodiments, filter the past temperature data to provide a more precise value, allow for a floating trip level that will change with the rate of temperature change and even allow for prediction of the amount of time left before a system shutdown may occur.