Abstract: A hand tool is used to drive a fastener about an axis, and includes a handle with an axially extending bore for receiving frictionally a fastener engaging member. The engaging member has an axially extending inner surrounding surface, and an inner peripheral wall which extends radially and inwardly to define a mounting hole communicating with the inner surrounding surface. A deformable member is inserted into the mounting hole, and has a protrusion extending inwardly of the inner surrounding surface when the engaging member is received in the handle. A bit, which includes two screwdriver tip ends and a shaft, is brought to be inserted into and is coupled to rotate with the engaging member axially such that the protrusion frictionally engages the shaft radially so as to hinder removal of the bit from the engaging member axially.

Abstract: A two terminal ESD protection structure formed by an alternating arrangement of adjacent p-n-p-n-p semiconductor regions provides protection against both positive and negative ESD pulses. When an ESD pulse appears across the two terminals of the ESD protection structure, one of the inherent n-p-n-p thyristors is triggered into a snap-back mode thereby to form a low impedance path to discharge the ESD current. Some embodiments of the ESD protection structure of the present invention have an enhanced current handling capability and are formed by combining a number of standard cells. The standard cells include a corner cell, a center cell and an edge cell which are arranged adjacent each other to form an ESD protection structure which provides for current flow from across many locations therein. Some embodiments of the ESD protection structure of the present invention include a network consisting of a pair of current sources, e.g.

Abstract: A redundancy circuit is capable of repeatedly replacing a defective cell with redundant cells. The redundancy circuit is in a semiconductor memory device that includes memory cells and redundant cells in a memory array. The redundancy circuit includes first and second fuse blocks. The first fuse block has a first main fuse and generates a first redundancy signal according to whether the first main fuse is cut. The first redundancy signal indicates whether there is a defective memory cell for the redundancy circuit to replace. The second fuse block has a second main fuse and generates a second redundancy signal according to whether the second main fuse is cut. The second redundancy signal can stop the replacement of the defective cell with the redundant cell when the redundant cell is defective. When the replacement of the defective cell with the redundant cell is stopped, the defective cell is replaced by another redundant cell.

Abstract: A method of manufacturing devices with source, drain and extension regions is provided. To achieve in the extensions a depth and dopant levels different from the source and drain regions, a channel-shaped oxide structure is formed surrounding a polysilicon gate. The channel-shaped oxide structures forms an implantation barrier over the extensions region. Thus, when the source and drain implantation is carried out at a given energy, the extension regions receives a 35-40 percent dopant dose, as compared to the dose received by the source region and the drain region.

Abstract: Provided is an amplifier circuit and method of using the same that features an adjustable resistor network to enable varying the operational characteristics of an amplifier. The resistor network includes primary resistors connected in series with a plurality of adjustment resistors connected to the output of an operational amplifier. A switching network is connected between the resistor network and the input of the operational amplifier. The switching network enables selectively varying the input and feedback resistance of the amplifier circuit to obtain a desired differential gain, while minimizing common-mode gain.

Abstract: A shallow abrupt junction is formed in a single crystal substrate, for example, to form a pn junction in a diode or a source drain extension in a transistor. An amorphous layer is formed at the surface of the substrate by implanting an electrically inactive ion, such as germanium or silicon, into the substrate. The amorphous/crystalline interface between the amorphous layer and the base crystal substrate is located at the depth of the desired junction. A dopant species, such as boron, phosphorus or arsenic is implanted into the substrate so that peak concentration of the dopant is at least partially within the amorphous layer. The amorphous layer can be formed either before or after the implanting of the dopant species. A low temperature anneal is used to recrystallize the amorphous layer through solid phase epitaxy, which also activates the dopant within the amorphous layer. The dopant located beneath the original amorphous/crystalline interface remains inactive.

Abstract: A flexible, evacuable storage bag has a storage portion, an airtight seal, and a one-way valve. The valve includes a strip sandwiched between top and bottom sheets used to make the bag. The strip is bonded along the edges to the top and bottom sheets so as to form a single passageway extending from the storage portion to outside the bag.

Abstract: A circuit for regulating a current provided by a power supply to drive a load in response to an input signal, is provided. The circuit contains a current source that has a specified current value and is coupled to the power supply. In addition, the circuit also comprises a controller that generates a reference voltage and is coupled to the current source. Furthermore, the circuit also includes a comparator that compares the reference voltage and a voltage at a node. To this node, controller is coupled. In addition, the load is coupled between the node and the power supply. In response to the input signal, the controller regulates the current to drive the load. This current has a first current-value that is proportional to the specified current value of the current source when the voltage at the node is greater than the reference voltage and a second current value that is based on the power supply when the voltage at the node is less than the reference voltage.

Abstract: Valve arrangement, in particular as pulse width modulated expansion valve of a refrigeration system, comprising the following elements: a valve body (1) with a passage opening (5), an armature tube (2) which is inserted into one end of the passage opening (5), an armature (3) which can be moved back and forth in the armature tube (2), a stationary armature core (4) which is inserted into the outwardly lying end of the armature tube (2), a restoring element (22) which is active between the movable armature (3) and the stationary armature core (4), a closure element (18) which is carried by the movable armature (3) and which cooperates with a passage opening (17) for opening and closing the valve arrangement as well as comprising a magnetic coil for actuating the valve arrangement, with a ring space (19) being formed between the armature tube (2) and the movable armature (3), the opening cross-section of which is dimensioned in such a manner that the space (20) which is formed between the movable armature (3) a

Abstract: An improved phase-locked loop circuit includes a variable-frequency oscillator that generates a first oscillator signal, a reference signal source that generates a second oscillator signal, a control block that generates a select signal, and a frequency divider that receives as an input signal one of the first and second oscillator signals. The frequency divider also receives the select signal from the control block. The frequency divider generates a plurality of frequency-divided signals in response to the input signal, and passes through a selected one of the plurality of frequency-divided signals as an output signal in response to the select signal. The frequency divider also synchronizes its output signal to its input signal. The phase-locked loop also includes a frequency comparator that receives the output signal of the frequency divider and a signal derived from one of the first and second oscillator signals.

Abstract: When a processing unit clock cycle period decreases (i.e., the processing unit operating frequency increases) such that the processing unit has only sufficient time to transfer accurately instruction fields from the instruction cache unit, the processing unit does not have sufficient time to determine the address of the next instruction to be retrieved from the instruction cache unit. In order to provide instruction fields to a pipelined processing unit with few breaks in the instruction field stream, the field in the program counter is incremented during to provide a speculative address of a next instruction field during a first clock cycle. During the first clock cycle, the instruction field identified by program counter field is accessed and transferred to the processor. The instruction field helps to determine an actual address of the next instruction field.

Abstract: An input/output circuit in an In-system programmable (ISP) logic device allows an output signal from a boundary scan register to be provided as output during programming operations of said ISP logic device. Thus, the ISP logic circuit can provide valid data output to other circuits interfaced to the ISP logic circuit during programming of the ISP logic device, thereby obviating a need to reset the system after reprogramming of the ISP logic device.

Abstract: The embodiments describe linear motor configurations having a polygonal shaped motor coil. The motor coil is e.g. hexagonal, diamond shaped, or double diamond shaped. Coil units are formed in a closed electrically conductive band surrounding a void. Coil units are formed e.g. from flex circuit material or by winding in a racetrack or folded tip fashion. Coil units are arranged in an overlapped shingle like manner to form a motor coil with substantially uniform thickness and high conductor density, providing high efficiency. Due to its substantially uniform thickness, the motor coil has a substantially flat cross section that allows the motor coil to be easily installed and removed from its associated linear magnetic track. The embodiments enable both moving coil and moving magnet linear motor configurations.

Abstract: A method, system and computer program product for automated technical support in a computer network having a client machine and at least one server. The method begins by selecting a diagnostic map useful in gathering diagnostic data for evaluating a given technical problem requiring diagnosis and correction. The diagnostic map encapsulates a set of one or more methods that, upon execution, explore the client machine and gather data. The diagnostic map is then executed by a diagnostic engine to generate a data set indicative of a current operating state of the client machine. This data set is forwarded from the client machine to the server for analysis. Based on the analysis performed at the server node, the data gathering process is repeated at the client machine, iteratively, until given information is available to a user of the client machine to correct the given technical problem.

Abstract: Two input binary signals are sampled in preparation for being encoded into one signal. The encoded signal is provided with one of the three discrete states based on the sample binary states of the two input signals. A first discrete state is provided if the sampled binary state of the first input signal is a first of two binary states. A second discrete state is provided if the sampled binary state of the first input signal is a second of two binary states, and if two sampled binary states of the second input signal are the same. A third discrete state is provided if the sampled binary state of the first input signal is a second of two binary states, and of the two sampled binary states of the second input signal are different. A corresponding decoding method is also described.

Abstract: A cathode structure suitable for a flat-panel display contains an emitter layer (213) divided into emitter lines, a plurality of electron emitters (229, 239, or 230) situated over the emitter lines, and a gate layer (215A) having an upper surface spaced largely above the electron emitters. The gate layer has a plurality of gate holes (215B) each corresponding to one of the electron emitters. The cathode structure further includes a carbon-containing layer (340, 240, or 241) coated over the electron emitters and directly on at least part of the upper surface of the gate layer such that at least part of the carbon-containing layer extending along and above the gate layer is exposed.

Abstract: In a nonvolatile memory, select gates are self-aligned spacers formed on sidewalls of floating/control gate stacks. The same mask (1710) is used to remove the select gate layer from over the source lines (144), to etch trench insulation in the source line regions, and to dope the source lines. The memory can be formed in and over an isolated substrate region. The source lines can be doped at least partially before the trench insulation is etched, to prevent a short before the source lines and a region isolating the isolated substrate region from below. The memory can be erased by sectors, or alternatively a chip erase operation can be performed to erase all the cells in parallel. Peripheral transistor gates can be formed from the same layer as the select gates. The select gate spacers have extensions to which low resistance contacts can be made from overlying metal lines.

Abstract: A computer system is provided that allows the content of a user's collection of fixed and removable media to be managed without regard to a specific type of media. The computer system performs equally well with files on floppy discs, removable hard-disks such as Iomega Zip, CDDA discs, CD-ROM discs, DVD-ROM discs and recordable or re-writeable variants of CD-ROMs and DVD-ROMs.

Abstract: A method and apparatus related to a data processing system contiguous-reference connection alignment mechanism. In one embodiment, an apparatus includes but is not limited to a data processing system contiguous-reference connection alignment mechanism, wherein the data processing system contiguous-reference connection alignment mechanism further includes but is not limited to a y-axis direction contiguous-reference alignment mechanism, wherein the y-axis direction contiguous-reference alignment mechanism further includes but is not limited to at least one fore-positioned data processing system connection guidance cylinder slot formed to catch a connection guidance cylinder misaligned in the y-axis direction and guide the connection guidance cylinder into substantial y-axis direction alignment. In one embodiment, a computer system includes but is not limited to a data processing system contiguous-reference alignment mechanism.

Abstract: A control circuitry for conveying video data in a flat panel display transmits video data using reduced swing differential signals that are time-multiplexed on a data bus. Data transmission schemes are provided to reduce data transitions on the data bus. A repeat last pixel scheme is used whenever the pixel data repeat horizontally on a display. A repeat last line pixel scheme is used whenever the pixel data repeat vertically on a display. A repeat last different pixel scheme is used whenever video data comprises mainly of monochrome information. In the alternate, a dynamic color pallet is used to store a few most frequently used pixel colors. When the current pixel color matches one of the colors stored, a pixel color address is transmitted instead of the pixel data itself. The use of reduced swing differential signaling on a time-multiplexed data bus together with one or more of the data transmission schemes achieves significant reduction in power consumption and electromagnetic interference generation.