Patents Represented by Attorney, Agent or Law Firm Skjerven Morrill MacPherson
  • Patent number: 6407458
    Abstract: A novel, moisture-resistant integrated circuit chip package is disclosed. In one embodiment, the integrated circuit chip package includes a substrate having a chip side and a backside. A first conductive layer is formed on the chip side of the substrate, and has a pattern forming conductive traces. A first soldermask layer is formed on the chip side of the substrate. The first soldermask layer directly contacts the first conductive layer. The first soldermask layer has at least one opening formed therein. A first contact layer is formed over the first conductive layer in the opening of the first. soldermask layer. A second conductive layer is formed on the backside of the substrate. A second soldermask layer is formed on the back side of the substrate and has at least one opening formed therein. A second contact layer overlies the second conductive layer in the opening of the second soldermask layer.
    Type: Grant
    Filed: May 4, 2000
    Date of Patent: June 18, 2002
    Assignee: Amkor Technology, Inc.
    Inventor: Ronald P. Huemoeller
  • Patent number: 6406953
    Abstract: Dynamic Random Access Memory (DRAM) cells are formed in a P well formed in a biased deep N well (DNW). PMOS transistors are formed in N wells. The NMOS channels stop implant mask is modified not to be a reverse of the N well mask in order-to block the channels stop implant from an N+ contact region used for DNW biasing. In DRAMS and other integrated circuits, a minimal spacing requirement between a well of an integrated circuit on the one hand and adjacent circuitry on the other hand is eliminated by laying out the adjacent circuitry so that the well is located adjacent to a transistor having an electrode connected to the same voltage as the voltage that biases the well. For example, in DRAMs, the minimal spacing requirement between the DNW and the read/write circuitry is eliminated by locating the DNW next to a transistor precharging the bit lines before memory accesses. One electrode of the transistor is connected to a precharge voltage.
    Type: Grant
    Filed: April 1, 1998
    Date of Patent: June 18, 2002
    Assignee: Mosel Vitelic, Inc.
    Inventors: Li-Chun Li, Huoy-Jong Wu, Chung-Cheng Wu, Saysamone Pittikoun, Wen-Wei Lo
  • Patent number: 6406641
    Abstract: A semiconductor process endpoint detection system uses a relatively wide wavelength range of light to reflect off a semiconductor wafer being processed. Relatively narrow wavelength ranges can be monitored within this wide reflected wavelength range in order to produce an endpoint of the process. An indication can be produced which is a function of detected light intensities at multiple wavelength ranges. These indications aid in the determination of an endpoint of a process.
    Type: Grant
    Filed: June 17, 1997
    Date of Patent: June 18, 2002
    Assignee: Luxtron Corporation
    Inventor: Reza Golzarian
  • Patent number: 6407779
    Abstract: The present invention discloses a novel universal remote control system. Specifically, the remote control system according to the present invention provides the following features: bidirectional communications between the remote control and at least one of the audio/video devices; dual communication mode; automatic communication mode selection; loading and processing electronic program guide in the remote control; soft graphical user interface in the remote control; expanding the television set functions by the remote control; calibration handshake between the remote control and the audio/video device; updating the remote control; lost beacon signal in the remote control; handwriting recognition mechanism, and voice recognition mechanism in the remote control.
    Type: Grant
    Filed: March 29, 1999
    Date of Patent: June 18, 2002
    Assignee: Zilog, Inc.
    Inventor: William S. Herz
  • Patent number: 6408026
    Abstract: A method for efficiently optimizing the bin widths for a distribution or an image to be compressed. An image having symmetric uni-modal distribution is divided into a zero bin having a zero bin width and a plurality of outer bins having an outer bin width. M numbers of predetermined candidate values for the zero bin width and N numbers of predetermined candidate values for the outer bin width are provided. A zero bin probability is derived from an entropy function. The allowable zero bin width is calculated from the zero bin probability and target bit rate. The allowable zero bin width is then searched to obtain an optimum combination of the zero bin width and the outer bin width, the optimum combination being the combination having the least distortion measure. In one embodiment, a fast algorithm is used to search the outer bin width for each given zero bin width, reducing the required combination by a factor of logN/N.
    Type: Grant
    Filed: August 6, 1999
    Date of Patent: June 18, 2002
    Assignees: Sony Corporation, Sony Electronics Inc.
    Inventor: Bo Tao
  • Patent number: 6407992
    Abstract: A method of multiplexing multiple terminals in a distributed network includes transporting user traffic and telephony signaling information. Transporting user traffic includes converting the user traffic into ATM cells, passing the ATM cells over a wireless link to a TDM port in an ATM multiplexer wherein the ATM multiplexer includes an ATM circuit emulation service, and converting the ATM cells into user traffic. Transporting telephony signaling information includes extracting the telephony signaling information from a user interface, passing the telephony signaling information to a base station using an ATM virtual circuit, processing and aggregating a number of telephony signaling information into a single channel, and transmitting the single channel to the ATM multiplexer.
    Type: Grant
    Filed: August 11, 2000
    Date of Patent: June 18, 2002
    Assignee: Netro Corporation
    Inventors: Eliezer Pasternak, Itai Aaronson, Gideon Ben-Efraim
  • Patent number: 6406934
    Abstract: The invention provides a manufacturing process for making chip-size semi-conductor packages (“CSPs”) at the wafer-level without the added size, cost, and complexity of substrates in the packages or the need to overmold them with plastic. One embodiment of the method includes the provision of a semiconductor wafer with opposite top and bottom surfaces and a plurality of dies integrally defined therein. Each die has an electronic device formed in a top surface thereof, and one or more electrically conductive vias extending therethrough that electrically connect the electronic device to the bottom surface of the die. The openings for the vias are formed ablatively with a laser and plated through with a conductive material. In a BGA form of the CSP, the vias connects the electronic device to lands on the bottom surface of the die. The lands may each have a bump of a conductive metal, e.g., solder, attached to it that functions as an input-output terminal of the CSP.
    Type: Grant
    Filed: September 5, 2000
    Date of Patent: June 18, 2002
    Assignee: Amkor Technology, Inc.
    Inventors: Thomas P. Glenn, Steven Webster, Vincent DiCaprio
  • Patent number: 6406636
    Abstract: Wafer-to-wafer bonding using, e.g., solder metal bonding, glass bonding or polymer (adhesive) bonding is improved by profiling one or both of the wafer surfaces being bonded to define microstructures therein. Profiling means providing other than the conventional planar bonding surface to define cavities therein. The bonding material fills the cavities in the microstructures. For instance, a system of ridges and trenches (e.g. in cross-section vertical, slanted, key-holed shaped, or diamond-shaped) are microstructures that increase the surface area of the wafers to which the bonding material can adhere. Use of the key-hole shaped or diamond-shaped profile having a negative slope at the trench interior substantially increases the bonding force.
    Type: Grant
    Filed: June 2, 1999
    Date of Patent: June 18, 2002
    Assignee: MegaSense, Inc.
    Inventor: Vladimir I. Vaganov
  • Patent number: 6407446
    Abstract: An aspect of the present invention provides a semiconductor chip package that can accommodate many outer leads in a relatively small package outline. The package includes a package body and outer leads along the outline of the package body. The package body outline has concave portions to increase the number of outer leads without increasing the package footprint. For example, the package can have a QFP outline with concave portions on the sides of the QFP outline. The package can have an SOP outline with concave portions on two opposite sides of the SOP outline.
    Type: Grant
    Filed: December 28, 2000
    Date of Patent: June 18, 2002
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Je Bong Kang, Jae Won Lee, Heui Seog Kim
  • Patent number: 6403897
    Abstract: A health care test kiosk includes a carrel body, a controller, a physiological test interface, a seat, and a weight scale. The carrel body supports a console housing and includes a support side panel forming a lateral side and extending beyond the console housing. The controller is housed within the console housing and includes a display and user interface. The physiological test interface is coupled to and supported by the carrel body on the support side panel. The physiological test interface is communicatively coupled to the controller for supplying physiological information to the controller for analysis and display. The seat is coupled to the support side panel of the carrel body. The weight scale is coupled to and supported by the seat. The weight scale is communicatively coupled to the controller for supplying weight information to the controller for analysis and display in combination with the physiological data.
    Type: Grant
    Filed: April 14, 2000
    Date of Patent: June 11, 2002
    Assignee: Computerized Screening, Inc.
    Inventors: Charles Bluth, James Bluth, Raymond G. Bryan, Jim C. Lovell, Richard L. Hicksted, Michael A. Spahr
  • Patent number: 6405060
    Abstract: An improved user interface for a cellular telephone system subscriber unit, including the following functions: (1) a predictive keyboard input method for speeding up input on a telephone with a space limited keyboard; (2) a word completion method for speeding up input; (3) a distinctive signaling method useful in a dual-mode or tri-mode cellular phone system that incorporates both voice call functionality and data messaging functionality; (4) a secret message method that permits secret messages to be received by an authorized user of a cellular telephone that includes a data messaging capability; (5) a message screening method that permits a user to set a message screening mode in a cellular telephone; (6) an improved “scratchpad” method which permits a user to enter a telephone number into a storage register of a cellular telephone while in the middle of a voice call, visually verify the entry, and then save the number to a rapid redial location for later use; (7) a global search method for searc
    Type: Grant
    Filed: December 19, 1997
    Date of Patent: June 11, 2002
    Assignee: Cirrus Logic, Inc.
    Inventors: Martin K. Schroeder, Duane Sharman
  • Patent number: 6404375
    Abstract: A digital calibration system for an analog-to-digital converter system includes a computational system receiving digital bits from an analog-to-digital converter representing selection of elements of the digital-to-analog converter in response to an analog input. The computational engine produces a digital output representative of the analog input during conversion operation, and digital values for adjustment of an adjustable analog source during calibration. Further, a digital system comprises a radix-less-than-two non-configurable digital-to-analog converter, a comparator system connected to the converter, and a computational system configured for SAR calibration and conversion.
    Type: Grant
    Filed: September 9, 1999
    Date of Patent: June 11, 2002
    Assignee: Cirrus Logic, Inc.
    Inventors: Carlos Esteban Muñoz, Karl Ernesto Thompson, Douglas S. Piasecki, Wai Laing Lee, Eric Swanson
  • Patent number: 6403501
    Abstract: A method is provided that conditions the chamber walls of a HDP CVD reactor by forming a layer of doped material prior to depositing dielectric layers of the doped material onto wafers. A consistent deposition rate can be maintained during subsequent deposition. When deposition is halted, the chamber is cleaned and a thin layer of the doped material is formed on the walls. Consequently, the chamber is kept at equilibrium even during periods of idle, thereby allowing the deposition rates to be consistent even after deposition resumes after the idle periods. For prolonged idle times, the chamber is re-cleaned and the doped material is re-deposited periodically, such as every 12 hours.
    Type: Grant
    Filed: December 27, 2000
    Date of Patent: June 11, 2002
    Assignee: Novellus Systems, Inc.
    Inventors: Jonathan W. Hander, Mahesh K. Sanganeria, Julian J. Hsieh
  • Patent number: 6405101
    Abstract: Disclosed is a system and method for detecting the position of a wafer with respect to a calibrated reference position. In one embodiment of the invention, sensors are used to detect the edges of the wafer as the wafer is being passed over the sensors. This wafer detection information is then used to calculate the amount by which the wafer is off-centered such that corrections can be made before the wafer is placed onto a destination location.
    Type: Grant
    Filed: November 5, 1999
    Date of Patent: June 11, 2002
    Assignee: Novellus Systems, Inc.
    Inventors: William R. Johanson, Craig Stevens, Steve Kleinke, Damon Genetti
  • Patent number: 6402843
    Abstract: The present invention relates to a non-contact holder for substantially planar workpieces, particularly suited for holding thin workpieces without substantial distortion. The present invention includes a cylindrical chuck having a gas inlet orifice positioned at an oblique. The introduction of pressurized gas creates a vortex and vacuum attraction holding a wafer in close proximity to the chuck while the gas exiting from the chuck prevents contact between wafer and chuck. Small diameter chucks located in close proximity help the present invention avoid distortion when processing very thin workpieces. The gas exiting from the chuck of the present invention exits preferentially in a certain angular direction. Chucks are arranged on the wafer holder such that exiting gas is preferentially directed radially towards the periphery of the holder and that exiting gas is directed between adjacent chucks, not directly at another nearby chuck.
    Type: Grant
    Filed: December 7, 1999
    Date of Patent: June 11, 2002
    Assignee: TruSi Technologies, LLC
    Inventors: Oleg Siniaguine, Sergey Savastiouk, Alex Berger, Igor Bagriy
  • Patent number: 6403209
    Abstract: A structure that is suitable for partial or full use in a spacer of a flat-panel display. The structure may be formed with a porous body having a face along which multiple primary pores extend into the porous body. A coating consisting primarily of carbon and having a highly uniform thickness overlies the porous body's face, extending along the primary pores to coat their surfaces and converting the primary pores into further pores. The coating can be created by removing non-carbon material from carbon-containing species provided along the pores. A solid porous film whose thickness is normally no more than 20 &mgr;m has a resistivity of 108-1014 ohm-cm. A spacer for a flat-panel display contains a support body and an overlying, normally porous, layer whose resistivity is greater parallel to a face of the support body than perpendicular to the body's face.
    Type: Grant
    Filed: December 11, 1998
    Date of Patent: June 11, 2002
    Assignees: Candescent Technologies Corporation, Candescent Intellectual Property Services, Inc., NanoPore Incorporated
    Inventors: Roger W. Barton, Michael J. Nystrom, Bob L. Mackey, Lawrence S. Pan, Shiyou Pei, Stephen Wallace, Douglas M. Smith
  • Patent number: 6404889
    Abstract: A VGA (or other component video signal) output, e.g. from a computer or DVD player, is protected so it is viewable on a VGA monitor. However, if the component video signal is converted to composite video (e.g. television) the resulting television picture is of substantially degraded quality, thereby inhibiting viewing and/or copying. This protects for instance copyrighted material in the VGA format from unauthorized use. The protection involves modifying the horizontal or vertical synchronization signals in the VGA video in such a way that there is no adverse affect on a typical VGA monitor. However, most or all VGA to television converters and/or television sets and VCR's suffer from loss of synchronization, resulting in an unviewable picture. Also, methods and circuits for defeating the copy protection are provided.
    Type: Grant
    Filed: October 13, 1997
    Date of Patent: June 11, 2002
    Assignee: Macrovision Corporation
    Inventors: John O. Ryan, Kordian J. Kurowski, Ronald Quan
  • Patent number: 6404020
    Abstract: A semiconductor device having a self-aligned contact pad and the method for manufacturing the device are disclosed. The semiconductor device includes: an isolation region formed in a semiconductor substrate; multiple conductive structures formed on the top surface of the semiconductor substrate; self-aligned conductive pads filling spaces between adjacent conductive structures and between the isolation region and the conductive structures. The method includes: forming a conductive structure on a semiconductor substrate; forming insulating sidewall spacers on the conductive structures, forming a conductive layer that fills spaces between the conductive structures and contacts the semiconductor substrate; and patterning the conductive layer.
    Type: Grant
    Filed: July 27, 1999
    Date of Patent: June 11, 2002
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Byeung-chul Kim
  • Patent number: 6404824
    Abstract: In order to reduce the noise components in a multiplexed communication system, noise components generally referred to as splatter that from the rapid transition between the transmitting state and the non-transmitting state, this power transition in the transmitted signal is provided with a ramped envelope. In the preferred embodiment, the ramped power transition is the result of a ramped enabling signal applied to the power amplifier generating the transmitted signal. The use of a ramped power transition reduces the noise introduced as a result of an abrupt power transition. In addition, the transmitted signal is provided with a preamble so that no data is transmitted during the transition period.
    Type: Grant
    Filed: December 16, 1998
    Date of Patent: June 11, 2002
    Assignee: Legerity, Inc.
    Inventors: Eddy Kent Bell, Stephen T. Janesch
  • Patent number: D458435
    Type: Grant
    Filed: July 11, 2000
    Date of Patent: June 11, 2002
    Assignee: Small Beginnings, Inc.
    Inventors: Mary S. Rogone, Philip N. Rogone