Abstract: A chip scale semiconductor package and a method for fabricating the package are provided. The package includes a semiconductor die and a flex circuit bonded to the face of the die. The flex circuit includes a polymer substrate with a dense array of external contacts, and a pattern of conductors in electrical communication with the external contacts. The package also includes interconnects configured to provide separate electrical paths between die contacts (e.g., bond pads), and the conductors on the flex circuit.

Abstract: A pass through test system for testing an electronic module includes an interface board, and metal fret test contactors configured to electrically engage, terminal contacts on the module. The test contactors and interface board are mounted to an automated or manual pass through test handler configured to allow electrical engagement of the module with a zero insertion force. The interface board includes interface contacts configured to engage the test contactors at intermediate points along their lengths, and to shorten the electrical paths through the test contactors. The interface contacts are in electrical communication with high speed conductors on the interface board, and can be constructed of a conductive polymer material, or alternately as metal frets. During a test method the module is supported edge to edge and generally parallel to the interface board.

Abstract: A pass through test system for testing an electronic module includes an interface board, and test contactors movably mounted to the interface board for electrically engaging terminal contacts on the module with a zero insertion force on the modules. The interface board is configured for mounting to an automated or manual pass through test handler in electrical communication with test circuitry. In a first embodiment the interface board includes test pads in electrical communication with the test circuitry, and rotatable test contactors having spring contacts configured to simultaneously engage the test pads and the terminal contacts on the module. In a second embodiment the interface board includes test pads in electrical communication with the test circuitry, and slidable test contactors having beam leads configured to simultaneously engage the test pads and the terminal contacts on the module.

Abstract: A method for fabricating an interconnect for testing semiconductor components forms contacts on a substrate configured to support and electrically engage bumped contacts on the components. Each contact includes a support member suspended on the substrate on cantilevered spring segment leads. The method includes the steps of forming a polymer material on the substrate, forming a metal layer on the polymer material and the substrate, forming the support member and leads in the metal layer, and then removing the polymer material to suspend the support member. In a first embodiment the polymer material fills a recess in the substrate and the support member is suspended on the recess. In a second embodiment the polymer material is formed as a bump, and the support member is suspended on a surface of the substrate.

Abstract: A bow resistant semiconductor package includes a semiconductor die, a leadframe and a plastic body. The plastic body includes a molded inner member encapsulating the die, and a molded outer member encapsulating the molded inner member. The inner member rigidities the package, and is dimensioned such that the outer member has substantially equal volumes of molding compound on either side of the leadframe. The equal volumes of molding compound reduce thermo-mechanical stresses generated during cooling of the molding compound, and reduce package bow. With reduced package bow, a planarity of the terminal leads on the package is maintained. Also, stresses on bonded connections between the terminal leads and electrodes on a supporting substrate, such as a printed circuit board or multi chip module substrate are reduced.

Abstract: A test carrier and an interconnect for testing semiconductor components, such as bare dice and chip scale packages, are provided. The carrier includes a base on which the interconnect is mounted, and a force applying mechanism for biasing the component against the interconnect. The interconnect includes interconnect contacts configured to make temporary electrical connections with component contacts (e.g., bond pads, solder balls). The interconnect also includes support members configured to physically contact the component, to prevent flexure of the component due to pressure exerted by the force applying mechanism. The support members can be formed integrally with the interconnect using an etching process. In addition, the support members can include an elastomeric layer to provide cushioning and to accommodate Z-direction dimensional variations.

Abstract: A method for singulating a substrate containing semiconductor components is performed using a nest for holding the substrate, a prestage alignment base for aligning the substrate during a prestage alignment step, and a vacuum cutting base for holding the nest and the substrate during a cutting step. The prestage alignment base includes locator pins configured to engage locator openings on the substrate to align the substrate on the nest. As the cutting base does not include the locator pins, the cutting step can be performed without saw scrap collecting on the locator pins. A system for performing the method includes the nest and the prestage alignment base having the locator pins configured to engage the locator openings on the substrate. The system also includes the sawing base which includes pedestals with vacuum conduits for holding the substrate stationary on the nest for sawing.

Abstract: A method for fabricating contacts on semiconductor components includes the steps of testing the components, and then using test data to fabricate the contacts on only components that meet a predetermined criteria. Initially a substrate, such as a wafer or a panel, containing multiple semiconductor components, such as dice or packages, is provided. The components include integrated circuits, and component contacts in electrical communication with the integrated circuits. In a first embodiment, a ball bumper apparatus programmed with the test data forms contact bumps on dice contained on a semiconductor wafer. In a second embodiment, a ball bumper apparatus programmed with the test data forms contact bumps on packages contained on a panel. In a third embodiment, a stencil mask is patterned with openings using a laser scanner programmed with the test data, and solder is stenciled into the openings, and reflow bonded to the component contacts to form contact bumps.

Abstract: A system for testing semiconductor components contained on a substrate, such as a wafer, a panel, a leadframe or a module, includes an interconnect configured to electrically engage all of the components on the substrate at the same time. The interconnect includes a switching network configured to selectively apply test signals to selected components, to electrically isolate defective components and to transmit test signals from selected groups of components. The system also includes a test apparatus, such as a wafer prober or a carrier for handling the substrate. A method for testing includes the steps of providing the interconnect having the switching network, and controlling test signals to the components using the switching network to perform various test procedures, such as functionality tests, parametric tests and burn-in tests.

Abstract: An interconnect for semiconductor components includes a substrate, and interconnect contacts on the substrate for electrically engaging component contacts on the components. The interconnect contacts include silicon carbide conductive layers, and conductors in electrical communication with the silicon carbide conductive layers. The silicon carbide conductive layers provides a wear resistant surface, and improved heat transfer between the component contacts and the interconnect contacts. The silicon carbide conductive layers can comprise doped silicon carbide, or alternately thermally oxidized silicon carbide. The interconnect can be configured for use with a testing apparatus for testing discrete components such as dice or chip scale packages, or alternately for use with a testing apparatus for testing wafer sized components, such as wafers, panels and boards. In addition, the interconnect can be configured for constructing semiconductor packages and electronic assemblies such as multi chip modules.

Abstract: A method and apparatus for aligning and connecting objects, such as semiconductor components and substrates, are provided. The apparatus includes a hexapod with a moving platform for holding an object for movement in six degrees of freedom. The apparatus also includes a chuck assembly for holding a mating object in a stationary position. A camera and a height gauge are mounted on the moving platform to allow determination of the position and orientation of the object on the chuck assembly. Likewise, a camera and a height gauge are mounted on the chuck assembly to allow determination of the position and orientation of the object on the moving platform. The hexapod includes linear actuators operable by a controller upon signal input from the cameras and height gauges. The apparatus can be used to electrically connect semiconductor dice and chip scale packages to interconnects for testing.

Abstract: A method for fabricating a semiconductor package is performed using a mold tooling fixture having a mold cavity and a pair of flash control cavities on either side of the mold cavity. The semiconductor package includes a substrate and a semiconductor die attached to the substrate. The substrate includes a pattern of conductors wire bonded to the die, and an array of solder balls bonded to ball bonding pads on the conductors. In addition, the substrate includes a die encapsulant encapsulating the die, and a wire bond encapsulant encapsulating the wire bonds. During molding of the wire bond encapsulant, the flash control cavities collect flash, and provide pressure relief for venting the mold cavity. In addition, the flash control cavities restrict the flash to a selected area of the package substrate, such that the ball bonding pads and solder balls are not contaminated.

Abstract: A molding apparatus for molding semiconductor components includes a pair of opposing mold chases having mating mold cavities. The mold cavities are configured to retain polymer release films for separating the molded components from the mold cavities. The molding apparatus also includes a movable pot having a reservoir for retaining a preform of molding compound, and a plunger for moving the molding compound into the mold cavities. The movable pot is mounted for axial movement within a chamfered opening in one of the mold chases. The movable pot is configured to clamp onto the release films to prevent wrinkling of the release films, and seepage of the molding compound under the release films. A system for molding semiconductor components includes the molding apparatus, a pot drive mechanism for moving the movable pot, a plunger drive mechanism for moving the plunger, and a clamping mechanism for clamping the mold chases together.

Abstract: A semiconductor carrier for testing semiconductor components, such as bare dice and chip scale packages, and a method for fabricating the carrier are provided. The carrier includes a molded plastic base, a lead frame, and an interconnect. The interconnect includes contacts for making temporary electrical connections with corresponding contacts (e.g., bond pads, solder balls) on the components. The carrier is fabricated by attaching the interconnect to the lead frame, and then molding the plastic base to the interconnect and lead frame. An alternate embodiment carrier includes a board to which multiple interconnects are molded or laminated. In addition, clip members retain the components on the board in electrical communication with the interconnects.

Abstract: A method and carrier for testing semiconductor dice such as bare dice or chip scale packages are provided. The carrier includes a base for retaining a single die, an interconnect for establishing temporary electrical communication with the die, and a force applying mechanism for biasing the die and interconnect together. In an illustrative embodiment the base includes conductors arranged in a universal pattern adapted to electrically connect to different sized interconnects. Interconnects are thus interchangeable on a base for testing different types of dice using the same base. The conductors on the base can be formed on a planar active surface of the base or on a stepped active surface having different sized cavities for mounting different sized interconnects. In an alternate embodiment the carrier includes an interposer. In a first interposer embodiment, the interposer connects directly to external test circuitry and can be changed to accommodate different sized interconnects.

Abstract: A BOC (board-on-chip) semiconductor package includes a semiconductor die having die contacts, a substrate bonded circuit side down to the die, and an adhesive layer bonding the substrate to the die. The substrate includes a circuit side having a pattern of conductors and wire bonding sites, and a back side having an array of external contacts (e.g., BGA solder balls) in electrical communication with the conductors. The bonding sites on the conductors overhang the peripheral edges of the substrate such that access is provided for bonding wires to the bonding sites and to the die contacts. Because the substrate is bonded circuit side down to the die, a loop height of the wires, and an overall height (profile) of the package are reduced by a thickness of the substrate. In addition, a planarity of molded segments that encapsulate the wires is improved, and mold bleed during molding of the molded segments is reduced.

Abstract: A method and system for fabricating solder bumps on semiconductor components are provided. The component can be a wafer, a die, a package, or a BGA substrate. The component is provided with electrodes, such as aluminum bond pads, on which the solder bumps are formed. Initially, the electrodes are cleaned and activated for a subsequent electroless deposition processes. Next, adhesion metal layers are electrolessly deposited on the electrodes to provide adhesion. and a barrier layer on the electrodes. Next, solder wettable layers are electrolessly deposited on the adhesion metal layers, to provide wettable surfaces for depositing the solder bumps. Preferred materials include nickel for the adhesion metal layers, and palladium for the solder wettable layers. A wave soldering process is then used to deposit solder bumps on the solder wettable layers.

Abstract: A method for fabricating semiconductor components, such as BGA packages, chip scale packages, and multi chip modules, includes the steps of cutting decals from ribbons of adhesive tape, and then attaching a semiconductor die to a substrate using the decals. A system for performing the method includes a tape cutting apparatus configured to cut the decals from the tape without wasted tape, and then to apply the cut decals to the substrate. A first finished dimension (e.g., width) of the decals is determined by a width of the tape, and a second finished dimension (e.g., length) of the decals is determined by indexing the tape through a selected distance. The tape cutting apparatus includes cutters configured to move through guide openings to cut and apply the decals to the substrate. The guide openings align the tape to the cutters, and also align the cut decals to the substrate. The system also includes a substrate handling apparatus configured to index and position the substrate relative to the guide openings.

Abstract: A method for testing and burning-in semiconductor components such as semiconductor dice on a semiconductor wafer, is provided. The method includes the step of providing all of the components on the wafer with resilient contact structures, such as metal pins having integral spring segments. The resilient contact structures are used to test the components to identify functional and non-functional components. Following this test, the resilient contact structures on the non-functional components are deformed, such that electrical communication with the non-functional components is prevented in a subsequent burn-in test. This permits the burn-in test to be performed using “shared resources” test equipment. A deformation apparatus for deforming the resilient contact structures includes a deformation block configured to compress, bend or shape the resilient contact structures on the non-functional dice.

Abstract: A method for fabricating semiconductor components and interconnects includes the steps of providing a substrate, such as a semiconductor die, forming external contacts on opposing sides of the substrate by laser drilling vias through the substrate, and forming conductive members in the vias. The conductive members include enlarged terminal portions that are covered with a non-oxidizing metal. The method can be used to fabricate stackable semiconductor packages having integrated circuits in electrical communication with the external contacts. The method can also be used to fabricate interconnects for electrically engaging packages, dice and wafers for testing or for constructing electronic assemblies.