Abstract: A semiconductor package includes a substrate and a semiconductor die wire bonded, or alternately flip chip bonded, to the substrate. The substrate includes three separate layers including a conductive layer having a pattern of conductive traces, a first insulating layer covering the conductive traces, and a second insulating layer covering the die. The insulating layers also include planar surfaces having external contacts, and conductive vias in electrical communication with the external contacts and with the conductive traces. The external contacts have matching patterns, such that the package can be stacked on a substantially identical package to form a stacked electronic assembly. In addition, the packages in the stacked assembly can have different circuit configurations, and can perform different functions in the assembly.

Abstract: An interconnect for testing semiconductor components includes a substrate, and interconnect contacts on the substrate for electrically engaging terminal contacts on the components. The interconnect also includes one or more cavities in the substrate which form flexible segments proximate to the interconnect contacts. The flexible segments permit the interconnect contacts to move independently in the z-direction to accommodate variations in the height and planarity of the terminal contacts. In addition, the cavities can be pressurized, or alternately filled with a polymer material, to adjust a compliancy of the flexible segments. Different embodiments of the interconnect contacts include: metallized recesses for retaining the terminal contacts, metallized projections for penetrating the terminal contacts, metallized recesses with penetrating projections, and leads contained on a polymer tape and cantilevered over metallized recesses.

Abstract: A pass through test system for testing an electronic module includes an interface board, and metal fret test contactors configured to electrically engage terminal contacts on the module. The test contactors and interface board are mounted to an automated or manual pass through test handler configured to allow electrical engagement of the module with a zero insertion force. The interface board includes interface contacts configured to engage the test contactors at intermediate points along their lengths, and to shorten the electrical paths through the test contactors. The interface contacts are in electrical communication with high speed conductors on the interface board, and can be constructed of a conductive polymer material, or alternately as metal frets. During a test method the module is supported edge to edge and generally parallel to the interface board.

Abstract: A semiconductor package, and a method for fabricating the package are provided. The package includes a semiconductor die, a lead frame, and a metal foil die mounting plate adapted to mount the die to the lead frame. In addition, the die mounting plate provides a thermally conductive path from the die to terminal leads of the package. Further, the die mounting plate can be configured to perform electrical functions, such as providing ground/power planes for the package, and adjusting an impedance of signal paths through the package. In a first embodiment the package can be fabricated using a tape under frame lead frame. In a second embodiment the package can be fabricated using a lead under chip lead frame.

Abstract: A pass through test system for testing an electronic module includes an interface board, and test contactors movably mounted to the interface board for electrically engaging terminal contacts on the module with a zero insertion force on the modules. The interface board is configured for mounting to an automated or manual pass through test handler in electrical communication with test circuitry. In a first embodiment the interface board includes test pads in electrical communication with the test circuitry, and rotatable test contactors having spring contacts configured to simultaneously engage the test pads and the terminal contacts on the module. In a second embodiment the interface board includes test pads in electrical communication with the test circuitry, and slidable test contactors having beam leads configured to simultaneously engage the test pads and the terminal contacts on the module.

Abstract: A method for fabricating semiconductor components is performed using a laser scanner and a laser imaging process. A substrate, such as a semiconductor wafer, containing multiple semiconductor components, such as dice or packages, is provided. The components include integrated circuits, and component contacts in electrical communication with the integrated circuits. Initially, the components are tested to identify and locate good components and defective components on the substrate. Using data from the testing step and the laser scanner, patterns of conductors are then formed to either repair the defective components, to electrically isolate the defective components for burn-in, or to form component clusters containing only the good components. Alternately, using data from the testing step and the laser scanner, a matching test board can be fabricated, and used to electrically engage the good components, while the defective components remain isolated.

Abstract: An interconnect for testing semiconductor wafers, and a method and system for testing wafers using the interconnect are provided. The interconnect includes a substrate with contact members configured to establish temporary electrical communication with contact locations (e.g., bond pads, test pads) on the wafer. For flat contact locations (e.g., thin film bond pads), the contact members comprise raised members with penetrating projections. For bumped contact locations (e.g., solder bumps), the contact members comprise indentations with a conductive layer. The interconnect also includes a pressure sensing mechanism for monitoring and controlling contact forces between the interconnect and wafer. In an illustrative embodiment the pressure sensing mechanism comprises a piezoresistive or piezoelectric layer and resistance measuring device.

Abstract: An interconnect, a test system, and a test method for testing bumped semiconductor components, such as dice and packages, contained on substrates, such as wafers or panels, are provided. The test system includes the interconnect, a tester for generating test signals, and a wafer prober for placing the components and interconnect in physical contact. The interconnect includes interconnect contacts, such as conductive pockets, for electrically engaging bumped component contacts on the components. The interconnect also includes an on board multiplex circuit adapted to fan out and selectively transmit test signals from the tester to the interconnect contacts. The multiplex circuit expands tester resources by allowing test signals to be written to multiple components in parallel. Reading of the test signals from the components can be performed in groups up to the limit of the tester resources.

Abstract: A chip scale semiconductor package and a method for fabricating the package are provided. The package includes a semiconductor die and a flex circuit bonded to the face of the die. The flex circuit includes a polymer substrate with a dense array of external contacts, and a pattern of conductors in electrical communication with the external contacts. The package also includes interconnects configured to provide separate electrical paths between die contacts (e.g., bond pads), and the conductors on the flex circuit.

Abstract: A method for testing and burning-in semiconductor components such as semiconductor dice on a semiconductor wafer, is provided. The method includes the step of providing all of the components on the wafer with resilient contact structures, such as metal pins having integral spring segments. The resilient contact structures are used to test the components to identify functional and non-functional components. Following this test, the resilient contact structures on the non-functional components are deformed, such that electrical communication with the non-functional components is prevented in a subsequent burn-in test. This permits the burn-in test to be performed using “shared resources” test equipment. A deformation apparatus for deforming the resilient contact structures includes a deformation block configured to compress, bend or shape the resilient contact structures on the non-functional dice.

Abstract: A semiconductor card includes a printed circuit substrate and one or more semiconductor components, such as dice or packages, mounted to the substrate. The substrate is initially a segment of a strip containing several substrates. The substrate is defined by a peripheral opening in the strip, and is connected to the strip by connecting segments. The card also includes a plastic body molded to the substrate and having notches that initially align with the connecting segments. The notches provide access for severing the connecting segments, and also enclose any slivers of substrate material resulting from severing of the connecting segments. A method for fabricating the package includes the steps of providing the strip, and providing a molding apparatus configured to mold the plastic body to the substrate. The molding apparatus includes pins configured to contact the connecting segments to form the notches.

Abstract: A contact system for electrically engaging semiconductor components includes an interface board mountable to an automated test handler, and a floating substrate on the interface board. The interface board includes interface contacts in electrical communication with external test circuitry. The substrate includes flexible segments, and contactors having contact pads on opposing sides of the flexible segments configured to simultaneously electrically engage terminal contacts on the components, and the interface contacts on the interface board. The contact pads include conductive polymer layers that provide an increased compliancy for the contactors. This increased compliancy allows the contactors to accommodate variations in the dimensions and planarity of the terminal contacts on the component. In addition, the substrate includes grooves between the contactors which provide electrical isolation and allow the contactors to move independently of one another.

Abstract: A semiconductor package includes a substrate and a semiconductor die wire bonded, or alternately flip chip bonded, to the substrate. The substrate includes three separate layers including a conductive layer having a pattern of conductive traces, a first insulating layer covering the conductive traces, and a second insulating layer covering the die. The insulating layers also include planar surfaces having external contacts, and conductive vias in electrical communication with the external contacts and with the conductive traces. The external contacts have matching patterns, such that the package can be stacked on a substantially identical package to form a stacked electronic assembly. In addition, the packages in the stacked assembly can have different circuit configurations, and can perform different functions in the assembly.

Abstract: A molding apparatus for molding semiconductor components includes a pair of opposing mold chases having mating mold cavities. The mold cavities are configured to retain polymer release films and also includes a movable pot having a reservoir for retaining a preform of molding compound, and a plunger for moving the molding compound into the mold cavities. The movable pot is mounted for axial movement within a chamfered opening in one of the mold chases. The movable pot is configured to clamp onto release films to prevent wrinkling of the release films, and seepage of the molding compound under the release films. A system for molding semiconductor components includes the molding apparatus, a pot drive mechanism for moving the movable pot, a plunger drive mechanism for moving the plunger, and a clamping mechanism for clamping the mold chases together.

Abstract: A bow resistant semiconductor package includes a semiconductor die, a leadframe and a plastic body. The plastic body includes a molded inner member encapsulating the die, and a molded outer member encapsulating the molded inner member. The inner member rigidities the package, and is dimensioned such that the outer member has substantially equal volumes of molding compound on either side of the leadframe. The equal volumes of molding compound reduce thermo-mechanical stresses generated during cooling of the molding compound, and reduce package bow. With reduced package bow, a planarity of the terminal leads on the package is maintained. Also, stresses on bonded connections between the terminal leads and electrodes on a supporting substrate, such as a printed circuit board or multi chip module substrate are reduced.

Abstract: An interconnect for testing semiconductor components having both bumped contacts, and planar contacts, is provided. The interconnect includes: a substrate, first contacts on the substrate for electrically engaging the bumped contacts, and second contacts on the substrate for electrically engaging the planar contacts. In illustrative embodiments the first contacts include recesses in the substrate covered with a conductive layer, or recesses formed in a compliant layer on the substrate, or conductive polymer donuts sized and shaped to retain the bumped contacts. In illustrative embodiments the second contacts include etched pillars having penetrating projections, or conductive polymer bumps having penetrating particles, or flat topped projections having a compliant layer thereon. The interconnect can be used to construct a die level test carrier for testing components in singulated form, or to construct a wafer level test carrier for testing components in wafer or panel form.

Abstract: A method for fabricating an interconnect with high aspect ratio contact members is provided. The interconnect is adapted to make electrical connections with a semiconductor component, such as a die, a wafer, or a chip scale package for testing. The method includes providing a substrate with projections, and forming a first conductive layer on the projections and substrate. The first conductive layer is then patterned using a resist mask having a thickness greater than a height of the projections. The resist mask can be a thick film resist that includes an epoxy resin, an organic solvent and a photo initiator. A second conductive layer is then formed on the projections, and patterned using a second resist mask having a thickness less than the height of the projections. Each contact member includes a projection with a tip portion having an exposed portion of the first conductive layer, and with a portion of the second conductive layer providing an electrical path to the projection.

Abstract: An interconnect for testing semiconductor components includes a substrate, and contacts on the substrate for making temporary electrical connections with bumped contacts on the components. Each contact includes a recess and a support member over the recess configured to electrically engage a bumped contact. The support member is suspended over the recess on spiral leads formed on a surface of the substrate. The spiral leads allow the support member to move in a z-direction within the recess to accommodate variations in the height and planarity of the bumped contacts. In addition, the spiral leads twist the support member relative to the bumped contact to facilitate penetration of oxide layers thereon. The spiral leads can be formed by attaching a polymer substrate with the leads thereon to the substrate, or by forming a patterned metal layer on the substrate. In an alternate embodiment contact, the support member is suspended over the surface of the substrate on raised spring segment leads.

Abstract: An interconnect, a test system, and a test method for testing bumped semiconductor components, such as dice and packages, contained on substrates, such as wafers or panels, are provided. The test system includes the interconnect, a tester for generating test signals, and a wafer prober for placing the components and interconnect in physical contact. The interconnect includes interconnect contacts, such as conductive pockets, for electrically engaging bumped component contacts on the components. The interconnect also includes an on board multiplex circuit adapted to fan out and selectively transmit test signals from the tester to the interconnect contacts. The multiplex circuit expands tester resources by allowing test signals to be written to multiple components in parallel. Reading of the test signals from the components can be performed in groups up to the limit of the tester resources.

Abstract: A calibration target for calibrating semiconductor wafer test systems including probe testers and probe card analyzers is provided. Also provided are calibration methods using the calibration target, and a method for fabricating the calibration target. The calibration target includes a substrate with various three dimensional alignment features formed thereon. A first type of alignment feature includes a contrast layer and an alignment fiducial formed on a tip portion thereof. The contrast layer and alignment fiducial are configured for viewing by a viewing device of the probe card analyzer, or the test system, to achieve X-direction and Y-direction calibration. A second type of alignment feature includes a conductive layer formed on a tip portion thereof, which is configured to electrically engage a contact on a check plate of the probe card analyzer, or a probe contact on a probe card of the test system, to achieve Z-direction calibration.