Patents Represented by Attorney, Agent or Law Firm Stephen B. Ackerman
  • Patent number: 6836526
    Abstract: A fractional-N frequency synthesizer has a modulus controller with multiple inputs that control an initial output frequency of the frequency synthesizer, an increment of variation of tuning of the frequency synthesizer, and a difference between two adjacent output frequency settings. The fractional frequency synthesizer includes a modulus controller, which controls the modulus factor for a multiple modulus frequency divider. The modulus controller has a modulus selection circuit that provides a modulus control signal to the modulus divider to select the modulus factor of the modulus divider as a function of a sum of one input factor and a product of a second input and the gain factor. Control signal is an overflow from a continuous summation of the second digital data word and a product of the first digital data word and the gain factor digital data word repetitively with itself.
    Type: Grant
    Filed: February 25, 2003
    Date of Patent: December 28, 2004
    Assignee: Agency for Science, Technology and Research
    Inventor: Ram Singh Rana
  • Patent number: 6836693
    Abstract: A new computer based method is provided for the evaluation of dielectric film properties. These properties are for a given dielectric derived from measurements of the chemical bonding of that dielectric. Previously collected reference data are maintained in a reference data base from where data are extracted and used as input to mathematical modeling software that predicts thin film properties. The output of these prediction algorithms is used, together with chemical bonding measurements of the dielectric that is being investigated, as input to a program that computers the dielectric properties of the dielectric.
    Type: Grant
    Filed: July 24, 2000
    Date of Patent: December 28, 2004
    Assignee: Industrial Technology Research Institute
    Inventor: Hung-Wen Chiou
  • Patent number: 6826015
    Abstract: A flux concentrating stitched write head design for high data rate applications is provided. The flux concentration is achieved by means of a non-magnetic step embedded into a portion of the lower magnetic pole of the write head, just beneath the write gap layer. The design permits extremely short throat heights, which will be required by future high data rate applications.
    Type: Grant
    Filed: June 3, 2003
    Date of Patent: November 30, 2004
    Assignee: Headway Technologies, Inc.
    Inventors: Mao-Min Chen, Pokang Wang, Cherng-Chyi Han
  • Patent number: 6825084
    Abstract: A method for making a twin MONOS memory array is described where two nitride storage sites lay under the memory cell word gate. The fabrication techniques incorporate self alignment techniques to produce a small cell in which N+ diffusion the nitride storage sites are defined by sidewalls. The memory cell is used in an NAND array where the memory operations are controlled by voltages on the word lines and column selectors. Each storage site within the memory cell is separately programmed and read by application of voltages to the selected cell through the selected word line whereas the unselected word lines are used to pass drain and source voltages to the selected cell from upper and lower column voltages.
    Type: Grant
    Filed: October 30, 2003
    Date of Patent: November 30, 2004
    Assignee: Halo LSI, Inc.
    Inventors: Seiki Ogura, Tomoko Ogura, Tomoya Saito, Kimihiro Satoh
  • Patent number: 6825520
    Abstract: A process for creating a storage node electrode, for a DRAM cell, exhibiting increased surface area resulting from the formation of an agglomerated metal silicide layer, on the top surface of the storage node electrode, has been developed. The process features creating a polysilicon, storage node electrode shape, followed by the formation of an overlying, agglomerated titanium disilicide layer. The agglomerated titanium disilicide layer is formed from a RTA procedure, applied to a smooth titanium disilicide layer, located on the polysilicon, storage node electrode.
    Type: Grant
    Filed: March 27, 2000
    Date of Patent: November 30, 2004
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Shau-Lin Shue, Cheng-Yeh Shih
  • Patent number: 6821892
    Abstract: A method is disclosed for accurately predicting the wet etch end points as a function of the temperature and concentration of the etching solution, as well as of the thickness of the film to be etched. This is accomplished by fitting an etch rate equation to the process of etching a film in terms of two constant parameters that are determined by one set of experiments performed on a given wet etch bench. Thereafter, the constants are used with the rate equation to calculate precisely the etch rate of a film, and then the etch rate is divided into a target film loss or a target film thickness to obtain etching time, or time to etch, which takes into account the variations in temperature and concentration, for example, of the acid in the solution. The resulting film either looses the specified amount of material, or acquires the specified thickness without incurring any damage, which is especially suited for sub-micron semiconductor technology where precise etching is required.
    Type: Grant
    Filed: June 4, 2001
    Date of Patent: November 23, 2004
    Assignee: Promos Technologies, Inc.
    Inventors: Chun Hong Peng, Rex Chen, Simon Chang
  • Patent number: 6822899
    Abstract: In the present invention a method and circuit are shown to protect flash memory from data corruption during a rapid power down. A circuit element detect the drop in power voltage and signals that any write operation being performed be switched into a programming phase, and at the same time increase the programming voltage to the flash memory to significantly reduce programming time. If the power drop occurs during an erase phase of a write operation, the erase operation is switched to a program operation using old data to program erased cells. If the power drop occurs during a programming phase of the write operation, the programming phase is continued but at a faster rate.
    Type: Grant
    Filed: December 23, 2002
    Date of Patent: November 23, 2004
    Assignee: Cypress Semiconductor Corporation
    Inventors: Khaled Boulos, Shailesh Shah, Carlos Awong
  • Patent number: 6819182
    Abstract: A method and circuits of a high isolation and high-speed buffer amplifier capable to handle frequencies in the GHz range have been achieved. The output to input isolation is primary dependent on the gate-source capacitance of the active buffer transistor. Having two or more in series and by reducing the impedance between them a high isolation can be achieved. The input signals are split in several signal paths and are amplified in the push-pull mode using source follower amplifiers. Then the amplified signals are being combined again. The amplified output current is mirrored applying a multiplication factor. Said method and technology can be used for buffer amplifiers having differential input and differential output or having single input and single output or having differential input and single output. A high reversed biased (output to input) isolation and a reduced quiescent current have been achieved.
    Type: Grant
    Filed: November 26, 2002
    Date of Patent: November 16, 2004
    Assignee: Dialog Semiconductor GmbH
    Inventor: Andreas Sibrai
  • Patent number: 6819589
    Abstract: A new method to detect and to correct a weakly programmed cell in a nonvolatile memory device is achieved. The method comprises providing a plurality of nonvolatile memory cells. A means to read a selected cell compares the performance of the selected cell with the performance of a reference cell. A read state of the selected cell is high if the selected cell exceeds the reference cell. The read state of the selected cell is low if the selected cell exceeds the reference cell. A first read state is obtained by reading the selected cell with the reference cell biased to a first value. A second read state is obtained by reading the selected cell with the reference cell biased to a second value that is greater than the first value. The selected cell is flagged as weakly programmed, high if the first and second read states do not match. A third read state is obtained by reading the selected cell with the reference cell biased to a third value that is less than the first value.
    Type: Grant
    Filed: May 15, 2003
    Date of Patent: November 16, 2004
    Assignee: Dialog Semiconductor GmbH
    Inventor: Thomas Aakjer
  • Patent number: 6818545
    Abstract: A barrier layer is deposited over a layer of passivation including in an opening to a contact pad created in the layer of passivation. A column of three layers of metal is formed overlying the barrier layer and aligned with the contact pad and having a diameter that is about equal to the surface of the contact pad. The three metal layers of the column comprise, in succession when proceeding from the layer that is in contact with the barrier layer, a layer of pillar metal, a layer of under bump metal and a layer of solder metal. The layer of pillar metal is reduced in diameter, the barrier layer is selectively removed from the surface of the layer of passivation after which reflowing of the solder metal completes the solder bump of the invention.
    Type: Grant
    Filed: March 5, 2001
    Date of Patent: November 16, 2004
    Assignee: Megic Corporation
    Inventors: Jin-Yuan Lee, Mou-Shiung Lin, Ching-Cheng Huang
  • Patent number: 6818491
    Abstract: In the present invention a method is shown that uses three concurrent word line voltages in memory cell operations of an a NOR type EEPROM flash memory array. A first concurrent word line voltage controls the operation on a selected word line within a selected memory block. The second concurrent word line voltage inhibits cells on non selected word lines in the selected memory block, and the third concurrent word line voltage inhibits non-selected cells in non-selected blocks from disturb conditions. In addition the three consecutive word line voltages allow a block to be erased, pages within the block to be verified as erased, and pages within the block to be inhibited from further erasure. The three consecutive voltages also allow for the detection of over erasure of cells, correction on a page basis, and verification that the threshold voltage of the corrected cells are above an over erase value but below an erased value.
    Type: Grant
    Filed: July 25, 2003
    Date of Patent: November 16, 2004
    Assignee: Aplvs Flash Technology, Inc.
    Inventors: Peter W. Lee, Hsing-Ya Tsao, Fu-Chang Hsu, Mervyn Wong
  • Patent number: 6818512
    Abstract: A multi-bit split-gate (MSG) flash cell with multi-shared source/drain and making of the same are disclosed. The MSG is formed with N+1 stacked gates comprising floating gates and control gates, separated by N select gates, all sharing the same source/drain between a pair of bit lines. With the disclosed MSG, a multiplicity of N+1 bit programming can be accomplished bit by bit where the programmed bits are selected by word line, bit line and control gate. In the erase operation, erased bits are selected by word line, while in the read operation, operations similar to write operation are performed. Thus, it is disclosed here that a plurality of N+1 bits or cells, where N is any integer, can be formed between two bit lines and along the same word line.
    Type: Grant
    Filed: January 4, 2002
    Date of Patent: November 16, 2004
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventor: Chia-Ta Hsieh
  • Patent number: 6819179
    Abstract: The load of the cascode amplifier is varied by connecting another (secondary) load in parallel with the original load. The secondary load is connected through a MOSFET switch. During the High Gain Mode the MOSFET switch is OFF and the secondary load is electrically isolated from the main load, whereas in the Low Gain Mode the switch is turned ON and the secondary load appears across the primary load, reducing the effective load impedance. The secondary load is AC coupled such that the DC bias current does not pass through the secondary load and hence the Noise Figure (NF) and linearity (IIP3) performance are better in the Low Gain Mode. A number of such switchable loads can be connected across the load to obtain programmability.
    Type: Grant
    Filed: April 16, 2003
    Date of Patent: November 16, 2004
    Assignee: Agency for Science, Technology and Research
    Inventors: Muthusamy Kumarasamy Raja, Nuntha Kumar Krishnasamy Maniam
  • Patent number: 6816346
    Abstract: As the dimensions of spin valve heads continue to be reduced, a number of difficulties are being encountered. One such is with the longitudinal bias when an external magnetic field can cause reversal of the hard magnet, thereby causing a hysteric response by the head. This coercivity reduction becomes more severe as the hard magnet becomes thinner. This problem has been overcome by inserting a decoupling layer between the antiferromagnetic layer that is used to stabilize the pinned layer of the spin valve itself and the soft ferromagnetic layer that is used for longitudinal biasing. This soft ferromagnetic layer is pinned by a second antiferromagnetic layer deposited on it on its far side away from the first antiferromagnetic layer. The presence of the decoupling layer ensures that the magnetization of the soft layer is determined only by the second antiferromagnetic layer. The inclusion of said decoupling layer allows more latitude in etch depth control during manufacturing.
    Type: Grant
    Filed: March 2, 2004
    Date of Patent: November 9, 2004
    Assignee: Headway Technologies, Inc.
    Inventors: You Feng Zheng, Kochan Ju, Cheng T. Horng, Simon Liao, Ru Ying Tong
  • Patent number: 6815337
    Abstract: A process for reducing the risk of removing metal from an underlying metal structure during a dry etch procedure used to define a borderless, overlying metal line structure, has been developed. After formation of a damascene type, underlying metal structure, deposition of an metal layer and of an overlying silicon oxide layer, is performed. A photoresist shape is used as an etch mask to allow formation of a partially etched metal line structure to be accomplished in the silicon oxide layer, and in a top portion of the metal layer. Insulator spacers are then formed on the sides of the partially etched metal line structure, resulting in a wider, partially etched metal line structure. The hard mask now presented by the defined silicon oxide component of the partially etched metal line structure, is then used as an etch mask allowing a final metal line structure, wider than the partially etched metal line structure, to be obtained.
    Type: Grant
    Filed: February 17, 2004
    Date of Patent: November 9, 2004
    Assignee: Episil Technologies, Inc.
    Inventor: Hsi Mao Hsiao
  • Patent number: 6815324
    Abstract: In accordance with the objectives of the invention a new method is provided for the creation of metal bumps over surfaces of I/O pads. Contact pads are provided over the surface of a layer of dielectric. The aluminum of the I/O pads, which have been used as I/O pads during wafer level semiconductor device testing, is completely or partially removed over a surface area that is smaller than the surface area of the contact pad using methods of metal dry etching or wet etching. The contact pad can be accessed either by interconnect metal created in a plane of the contact pad or by via that are provided through the layer of dielectric over which the contact pad has been deposited. The process can be further extended by the deposition, patterning and etching of a layer of polyimide over the layer of passivation that serves to protect the contact pad.
    Type: Grant
    Filed: February 15, 2001
    Date of Patent: November 9, 2004
    Assignee: MEGIC Corporation
    Inventors: Ching-Cheng Huang, Chuen-Jye Lin, Ming-Ta Lei, Mou-Shiung Lin
  • Patent number: 6809935
    Abstract: A new method is provided for mounting a semiconductor on the surface of a Printed Circuit Board. A layer of Elastomer is deposifed on the surface face of the PCB, this layer of Elastomer makes the PCB into a thermally compliant PCB such that the thermal mismatch between the PCB and the semiconductor die that is mounted on the PCB is sharply reduced. Openings are created in the layer of Elastomer and electrical interfaces are created such that the PCB can be connected to the semiconductor die that is mounted on the PCB.
    Type: Grant
    Filed: October 10, 2000
    Date of Patent: October 26, 2004
    Assignee: Megic Corporation
    Inventor: Jin-Yuan Lee
  • Patent number: 6808644
    Abstract: A process to form a capillary that is well insulated from its environment is described. Said process has two stages. The first stage, which is the same for both of the invention's two embodiments, comprises forming a micro-channel in the surface of a sheet of glassy material. For the first embodiment, this sheet is bonded to a layer of oxide, that lies on the surface of a sheet of silicon, thereby sealing in the capillary. After all silicon has been selectively removed, a thin membrane of oxide remains. Using a low temperature bonding process, a second sheet of glassy material is then bonded to this membrane. In the second embodiment, the silicon is not fully removed. Instead, the oxide layer of the first embodiment is replaced by an oxide/nitride/oxide trilayer which provides improved electrical insulation between the capillary and the remaining silicon at a lower level of inter-layer stress.
    Type: Grant
    Filed: May 2, 2002
    Date of Patent: October 26, 2004
    Assignee: Institute of Microelectronics
    Inventors: Yu Chen, Janak Singh
  • Patent number: 6806136
    Abstract: The present invention relates generally to semiconductor fabrication and more specifically to simultaneous formation of capacitors, resistors and metal oxide semiconductor.
    Type: Grant
    Filed: February 17, 2004
    Date of Patent: October 19, 2004
    Assignee: Episil Technologies, Inc.
    Inventor: Hsiu-Wen Hsu
  • Patent number: 6806570
    Abstract: A thermally compliant multi-layer wiring structure on a semiconductor chip is described. The multi-layer wiring structure incorporates an “empty” or air gap under the interconnect wiring and does not allow any thermally induced strains to be transmitted to the interconnecting solder balls. This design is to be used in chip scale packaging applications where printed circuit technology is used as the next level of package.
    Type: Grant
    Filed: October 24, 2002
    Date of Patent: October 19, 2004
    Assignee: Megic Corporation
    Inventors: Jin-Yuan Lee, Eric Lin