Abstract: The present invention relates generally to semiconductor fabrication and more specifically to simultaneous formation of capacitors, resistors and metal oxide semiconductor.

Abstract: A method of forming a device, comprising the following steps. A wafer holder and inner walls of a chamber are coated with a seasoning layer The wafer is placed upon the wafer holder and is cleaned wherein a portion of the seasoning layer is re-deposited upon the wafer over and between adjacent wafer conductive structures. The wafer is removed from the chamber and at least two adjacent upper metal structures are formed over at least one portion of a metal barrier layer. The exposed portions of the metal barrier layer are etched and removed, exposing portions of the re-deposited seasoning layer portions using the metal barrier layer etch process which also removes any exposed portions of the re-deposited seasoning layer portions that are comprised of a material etchable in the metal barrier layer etch process.

Abstract: The present invention relates to a nonvolatile memory cell and/or array and a method of operating the same high integrated density nonvolatile memory cell enabling high integration density, low voltage programming and/or high speed programming, a method of programming same and a nonvolatile memory array. A p-well 101 is formed in a surface of a substrate 10 and a channel forming semiconductor region 110 is defined in a surface of the p-well 101 and separated by a first n+ region 121 and a second n+ region 122. A carrier-supplying portion (CS: carrier supply) 111 is formed coming into contact with the first n+ region 121 and a carrier-acceleration-injection portion 112 (AI: acceleration and injection) is in contact with the second n+ region 122 in the channel forming semiconductor region 110 wherein the carrier-supplying portion 111 and carrier-acceleration-injection portion 112 are in contact with each other.

Abstract: The invention refers to a charge/discharge protection circuit for a rechargeable battery being able to differentiate between a temporary overvoltage on the charge/discharge terminals and a permanent overvoltage and in the last case for security reasons to permanently disconnect the battery from the charge/discharge terminals. Hereby said protection circuit comprises a number of partial switches (15[1:]), being either parallel to a load switch (LS) or parallel to the charge terminals, and an overvoltage detector (10) which closes in case of an overvoltage all partial switches via a control logic (11, 12, 13, 17, 18) and which afterwards opens one partial switch after the other. A voltage detector (16), monitoring the remaining voltage over the partial switches, inhibits, however, the opening of at that time next partial switch if the remaining voltage over the still closed partial switches is higher than a predefined limit of said remaining voltage.

Abstract: A multiple level logic memory device is achieved. The device comprises, first, a plurality of memory cells capable of storing an analog voltage. Second, there is included a means of converting an external data word value comprising one value of a set of at least three possible values into a writing analog voltage corresponding to the external data word value. Third, a means of decoding an external address value in response to a write command such that the writing analog voltage is electrically coupled to the memory cell is included. Fourth, there is included a means of converting the memory cell analog voltage into an external data word value comprising one value of the set of at least three possible values corresponding to the memory cell analog voltage. Finally, a means of encoding the external address value in response to a read command such that the memory cell analog voltage is electrically coupled to the means of converting the memory cell analog voltage is used.

Abstract: CVD dielectric materials are generally preferred for anti-reflection coatings because their optical properties can be varied both by controlling composition and by suitable surface treatment. In prior art films of this type it can be difficult to control both the refractive index and the extinction coefficient simultaneously. The present invention shows how optical properties can be tailored to meet a range of predetermined values by depositing each dielectric anti-reflection coating as a series of sub-coatings. After each sub-coating has been deposited it is subjected to surface treatment through exposure to a gaseous plasma, thereby forming an interface layer which provides a wider window for fine tuning RI and K values. Generally the finished film will comprise 3-of these sub-coatings. Software simulation is used to determine the precise composition for each sub-layer as well as the optical properties of the DARC film.

Abstract: Electrostatic discharge (ESD) protection for circuits which utilize multiple power supply rails, both positive (Vdd) and negative (Vss). Vdd busses remain completely isolated, while Vss busses are joined by pairs of complementary polarity diodes (made typically with P+/N-well diodes in an N/P-substrate process) thus keeping Vss busses isolated from each other. The I/O diodes of high frequency I/O pads are arranged in a square layout to achieve the best current/capacitance ratio. Each pair of power rails is provided with its own power shunt circuit, placing each shunt in physical proximity to the I/O pad it must protect. Shunts are designed to clamp at a very low voltage during an ESD event using mostly PMOS transistors. The protection circuit is laid out such that the worst case ESD event will flow at most between two I/O pads and one power shunt.

Abstract: This invention provides a method of using an electron beam exposure system having an electron beam with a variable shape to form patterns in a layer of resist on a substrate, a mask substrate or an integrated circuit wafer, while maintaining adequate critical dimension control and beam stability. This is accomplished by setting the electron beam to a fixed square beam with a width set to provide optimum XY critical dimension control for exposing a frame pattern surrounding the original pattern. The frame pattern has a width of a first distance and surrounds the outer perimeter of the original pattern. This provides optimum XY critical dimension control at the outer perimeter of the original pattern. The remainder of the exposure field, which is the exposure field with the original pattern and the frame pattern subtracted away is exposed using an electron beam having a variable size and shape.

Abstract: Apparatus and methods for testing an active pixel sensor ensure that a signal proportional to the quantity of light energy impinging on the active pixel sensor is reliably and accurately captured and made available for further on processing the rest of the APS system circuitry. The apparatus and method determines the capacitance of a photo-conversion device of the active pixel sensor. The apparatus and method determines that an active pixel sensor is functioning correctly. The apparatus and method determines the performance of an active pixel sensor. Where the performance of the active pixel sensor is a measure of linearity of the active pixel sensor and a connected chain of circuitry that process the signal converted by the photo-conversion device of the active pixel sensor.

Abstract: A method for forming a magnetoresistive (MR) sensor element. There is first provided a substrate. There is then formed over the substrate a seed layer. There is then formed contacting a pair of opposite ends of the seed layer a pair of patterned conductor lead layer structures. There is then etched, while employing an ion etch method, the seed layer and the pair of patterned conductor lead layer structures to form an ion etched seed layer and a pair of ion etched patterned conductor lead layer structures. Finally, there is then formed upon the ion etched seed layer and the pair of ion etched patterned conductor lead layers structures a magnetoresistive (MR) layered structure. Within the magnetoresistive (MR) sensor element, the pair of patterned conductor lead layer structures may be formed within a pair of recesses within an ion etch recessed dielectric isolation layer.

Abstract: A method to reduce clock noise in a multiple clock circuit is achieved. The method comprises, first, providing a periodic signal. Next, a first clock signal is provided having a frequency that is a constant multiple of the frequency of the periodic signal. Finally, a second clock signal is derived from the periodic signal. The second clock signal has a frequency that is a non-constant multiple of the periodic signal frequency. The non-constant multiple comprises the sum of a constant value plus a time-varying value. The spectral energy at the sum and difference frequencies of the first and second clock signals is reduced by frequency distribution spreading. A circuit is achieved comprising the above method.

Abstract: A method for creating a self-aligned channel implant with elevated source/drain areas. Forming a thin dielectric layer on top of a silicon substrate, a thick layer of oxide is deposited over this dielectric. An opening is exposed and etched through the layer of oxide, through the dielectric and into the underlying silicon substrate creating a shallow trench in the substrate. By performing the channel implant LDD implant, pocket implant, forming the gate spacers and electrode, removing the thick layer of oxide and forming the S/D regions a gate electrode has been created with elevated S/D regions. By forming the gate spacers, performing channel implant, forming the gate electrode, removing the thick layer of oxide and performing S/D implant a gate electrode has been created with elevated S/D regions and disposable spacers.

Abstract: A chip package for semiconductor chips is provided by the method of forming a chip package includes the steps of forming a printed circuit board with a window therethrough; forming semiconductor chip connections of one or more primary chips which overlie the window to the printed circuit board by solder connections, locating a suspended semiconductor chip within the window, and connecting the suspended semiconductor chip to one or more primary chips overlying the window in a chip-on-chip connection. A bypass capacitor is formed on the printed circuit board.

Abstract: A charge/discharge protection circuit with n parallel load current switches and a control logic for the latter, which in an over-voltage event disconnects the battery from the charge/discharge terminals through sequentially controlled melting of integrated fusible links, where the control logic in an over-voltage event, simultaneously closes all load current switches, then following sequentially opens a first number of the load current switches, and at the same time closes the switch segments of a short-circuit switch array associated with the respective load current switch, so that the associated fusible links melt sequentially. After the opening of this first number of load current switches the latter closes again and at the same time the remaining number of still closed load current switches opens, as well as continues to sequentially close the remaining switch segments.

Abstract: In the present invention is disclosed a flash memory for simultaneous read and write operations. The memory is partitioned into a plurality of sectors each of which have a sector decoder. The sector decoder connects a plurality of main bit lines to a plurality of sub bit lines contained within each memory sector A 21 decoder is used to demonstrate the invention although other decoders including a 2M decoder and a hierarchical type decoder can be used. The memory array can be configured from a variety of architectures, including NOR, OR, NAND, AND, Dual-String and DINOR. The memory cells can be formed from a variety of array structures including ETOX, FLOTOX, EPROM, EEPROM, Split-Gate, and PMOS.

Abstract: A circuit and method are given, to realize a high voltage comparator, which generates an output signal for follow-up processing in the low-voltage domain. The high-voltage comparison task is essentially replaced by a current comparison, implemented as a combination of a voltage to current transforming stage with a CMOS current comparator circuit, where only very few parts are working in the high voltage domain. Using the intrinsic advantages of that solution the circuit of the invention is manufactured with standard CMOS technology and only four discrete or integrated extended drain MOS components at low cost. This solution reduces the complexity of the circuit and in consequence also power consumption and manufacturing cost.

Abstract: A method for fabricating a longitudinally hard biased, bottom spin valve GMR sensor with a lead overlay (LOL) conducting lead configuration and a narrow effective trackwidth. The advantageous properties of the sensor are obtained by providing two novel barrier layers, one of which prevents oxidation of and Au diffusion into the free layer during annealing and etching and the other of which prevents oxidation of the capping layer during annealing so as to allow good electrical contact between the lead and the sensor stack.

Abstract: A method and a structure for a parasitic bipolar silicided ESD device that has high resistivity regions within the collector of the parasitic NPN. The device has the structure of a N-MOS transistor and a substrate contact. The device preferably has silicide regions over the doped regions. The invention has two types of high resistivity regions: 1) isolation regions (e.g., oxide shallow trench isolation (STI)) and 2) undoped or lightly doped regions (e.g., channel regions). The channel regions can have gates thereover and the gates can be charged. Also, optionally a n−well (n minus well) can be formed under the collector. The high resistivity regions increase the collector resistivity thereby improving the performance of the parasitic bipolar ESD device.

Abstract: A method and system for the design of an electronic device adjusts the resistance and capacitance values employed in preliminary timing analysis during physical synthesis of the electronic device. The physical synthesis uses resistance and capacitance unit values to determine the listing of the component circuits. The resistance and capacitance unit values are calibrated by preliminarily placing the initially synthesized component circuits to create a listing describing physical locations of the component circuits within the electronic device. A preliminary routing of the interconnections is performed to create a listing describing a network of physical wire segments that form each interconnection of the component circuits. A timing analysis of the electronic device determines the delay created by the component circuit and the networks of physical wire segments.

Abstract: An ESD device and method using parasitic bipolar transistors that are silicided. The first embodiment is a parasitic Bipolar Junction Transistor comprised of n+/n−/p−/n−/n+ regions. The emitter is formed of the second N+ region and the second N− well. The parasitic base is formed by the p− substrate or well. The collector is formed of the first well and the first n+ region. The benefit of the first embodiment is the trigger voltage is lower because the junction between the n− well (emitter) and P− substrate (base) and the junction between P− substrate (base) and the n-well have lower cross over concentrations. The second embodiment is similar to the first embodiment with the addition of the first gate. The first gate is preferably connected to the first n+ region and the Vpad. The third embodiment contains the same elements as the second embodiment with the addition of a third n+ region.