Abstract: A magnetic read head with reduced side reading characteristics is described. This design combines use of a current channeling layer (CCL) with stabilizing longitudinal bias layers whose magnetization direction is canted relative to that of the free layer easy axis and that of the pinned layer (of the GMR). This provides several advantages: First, the canting of the free layer at the side region results in a reduction of side reading by reducing magnetic sensitivity in that region. Second, the CCL leads to a narrow current flow profile at the side region, therefore producing a narrow track width definition. A process for making this device is described. Said process allows some of the requirements for interface cleaning associated with prior art processes to be relaxed.

Abstract: A new optical lithographic exposure apparatus is described. The apparatus may comprise, for example, a lithographic stepper or scanner. A wafer stage comprises a means of supporting a semiconductor wafer. A mask stage comprises a means of holding a first mask and a second mask and maintaining a fixed relative position between the first mask and the second mask. The mask stage may further comprise an independent means of aligning each mask. A light source comprises a means to selectively shine actinic light through one of the first mask and the second mask. An imaging lens is capable of focusing the actinic light onto the semiconductor wafer. A step and scan method using the mask stage is provided. A first mask and a second mask are loaded into a mask stage of an optical lithographic exposure apparatus. The first mask and the second mask are aligned. The first mask is scanned. The wafer is then stepped. The second mask is scanned.

Abstract: A new software support package is provided that monitors tool status and scheduling requirements in a semiconductor manufacturing environment. A multiplicity of tools interfaces with a Manufacturing Execution system (MES) that is a functional component of the Operation and supervision integrated MES user Interface (OMI). A User Interface (UI) function, which is also part of the OMI, interfaces between a multiplicity of users (of the OMI functions) and the MES sub-component of the OMI system.

Abstract: A new method of creating a relatively thick layer of PE silicon nitride. A conventional method of creating a layer of silicon nitride applies a one-step process for the creation thereof. Film stress increases as the thickness of the created layer of PE silicon nitride increases. A new method is provided for the creation of a crack-resistant layer of PE silicon nitride by providing a multi-step process. The main processing step comprises the creation of a relatively thick, compressive film of PE silicon nitride, over the surface of this relatively thick layer of PE silicon nitride is created a relatively thin (between about 150 and 500 Angstrom) layer of tensile stress PE silicon nitride. This process can be repeated to create a layer of PE silicon nitride of increasing thickness.

Abstract: A method of planarizing wafers using shallow trench isolation is described. The method uses a very hard polishing pad and chemical mechanical polishing with no additional etching required. Trenches are formed in a substrate and filled with a trench dielectric, such as silicon dioxide deposited using high density plasma chemical vapor deposition. A layer of resist is then formed on the layer of trench dielectric. The wafer is then planarized using chemical mechanical polishing and a polishing pad having a hardness of at least Shore “D” 52. The hard polishing pad avoids scratch marks on the trench dielectric, the substrate surface, or any other materials deposited on the substrate surface.

Abstract: A method for tracking the MOS oxide thickness by the native threshold voltage of a “native” MOS transistor without channel implantation for the purpose of compensating MOS capacitance variations is achieved. The invention makes use of the fact that in MOS devices the threshold voltage is proportionally correlated to the oxide thickness of said MOS device. Said threshold voltage can therefore be used to build a reference voltage Vx+Vth which accurately tracks the MOS capacitance variations in integrated circuits. Circuits are achieved to create a frequency reference and a capacitance reference using said method. Additionally a method is introduced to create a capacitance reference in integrated circuits using said MOSFET capacitors.

Abstract: A method for forming an NiCr seed layer based bottom spin valve sensor element having a synthetic antiferromagnet pinned (SyAP) layer and a capping layer comprising either a single specularly reflecting nano-oxide layer (NOL) or a bi-layer comprising a non-metallic layer and a specularly reflecting nano-oxide layer and the sensor element so formed. The method of producing these sensor elements provides elements having higher GMR ratios and lower resistances than elements of the prior art.

Abstract: A method for forming an antifuse interconnect structure, for a one-time fusible link, with field-programmable gate arrays, has been developed. The process features the use of an amorphous silicon layer, used as the antifuse layer, with the sidewalls of the amorphous silicon layer protected by critical silicon nitride sidewall spacers, during the patterning/etch procedure of the overlying metal layer. The protective sidewall spacers prevent the amorphous Si antifuse from being etched by subsequent processes.

Abstract: A method of forming a FINFET CMOS device structure featuring an N channel device and a P channel device formed in the same SOI layer, has been developed. The method features formation of two parallel SOI fin type structures, followed by gate insulator growth on the sides of the SOI fin type structures, and definition of a conductive gate structure formed traversing the SOI fin type structures while interfacing the gate insulator layer. A doped insulator layer of a first conductivity type is formed on the exposed top surfaces of a first SOI fin type shape, while a second doped insulator layer of a second conductivity type is formed on the exposed top surfaces of the second SOI fin type shape.

Abstract: A method to linearize the characteristic of a Class-D amplifier is achieved, by compensating for the pulse-area-error, caused by a non-constant power-supply and similar circuit inconsistencies. A Class-D Amplifier typically converts the PDM (Pulse Density Modulated) input signal with a Sigma Delta Modulator and typically uses an H-Bridge as the Class-D power output stage. A fundamental idea is to keep the time-voltage area of every pulse constant. To achieve this, the circuit integrates the power supply voltage, starting with the PDM input pulse and stopping, when the defined time-voltage reference is reached. To compensate not only for power supply variations, but also for e.g. the voltage drop across the output devices, the integrator's input would be more directly reference to the actual voltage across the output load.

Abstract: A method for forming within a substrate employed within a microelectronics fabrication an electrical interconnection cross-over bridging between conductive regions separated by non-conductive regions formed within the substrate. There is formed over a substrate provided with conductive and non-conductive regions a blanket dielectric layer and a blanket polysilicon layer. After patterning the polysilicon and dielectric layers. A portion of the dielectric layer at the periphery of the polysilicon layer is etched away, leaving a gap between the polysilicon patterned layer and the underlying substrate contact region. There is formed over the substrate a layer of refractory metal and after rapid thermal annealing, there is formed a surface layer of refractory metal silicide over the surfaces of the polysilicon layer and within the gap between the polysilicon layer and the substrate, completing the electrical connection.

Abstract: An under bump metallurgy (UBM) structure is described. Two UBM mask processes are utilized. First, a top layer of copper (Cu) and/or a middle layer of nickel-vanadium (NiV) or chrome-copper (CrCu) is personalized by standard photoprocessing and etching steps utilizing a bump based size mask. This is followed by patterning an underlying seed layer with a second, larger mask, thereby preventing damage to the aluminum cap and seed layer undercut during the etching process.

Abstract: P-type LDMOS devices have been difficult to integrate with N-type LDMOS devices without adding an extra mask because the former have been unable to achieve the same breakdown voltage as the latter due to early punch-through. This problem has been overcome by preceding the epitaxial deposition of N− silicon onto the P− substrate with an additional process step in which a buried N+ layer is formed at the surface of the substrate by ion implantation. This N+ buried layer significantly reduces the width of the depletion layer that extends outwards from the P− well when voltage is applied to the drain thus substantially raising the punch-through voltage.

Abstract: A new method is provided to remove the conventional accumulation of a layer of tin oxide over the surface of solder bumps by means of fluorine based plasma treatment of the solder bumps. In addition, an improved method is provided for the application of underfill that replaces the conventional method of providing an underfill for a packaged flip chip device.

Abstract: A Spin Valve GMR and Spin Filter SVGMR configuration where in the first embodiment an important buffer layer is composed of an metal oxide having a crystal lattice constant that is close the 1st FM free layer's crystal lattice constant and has the same crystal structure (e.g., FCC, BCC, etc.). The metal oxide buffer layer enhances the specular scattering. The spin valve giant magnetoresistance (SVGMR) sensor comprises: a seed layer over the substrate. An important metal oxide buffer layer (buffer layer) over the seed layer. The metal oxide layer preferably is comprised of NiO or alpha-Fe2O3. A free ferromagnetic layer over the metal oxide layer. A non-magnetic conductor spacer layer over the free ferromagnetic layer. A pinned ferromagnetic layer (2nd FM pinned) over the non-magnetic conductor spacer layer and a pinning material layer over the pinned ferromagnetic layer. In the second embodiment, a high conductivity layer (HCL) is formed over the buffer layer to create a spin filter -SVGMR.

Abstract: A new method and sequence is provided for the polishing of the surface of a layer of metal containing copper. The invention provides for an improved method of residue removal. The invention improves the removal of slurry as part of the step of applying DIW by, during the step of applying DIW, raising the wafer carrier, thus allowing uninhibited removal of the slurry from the surface that is being polished.

Abstract: Write head coils for magnetic disk systems are commonly formed through electroplating onto a seed layer in the presence of a photoresist mask. It is then necessary to remove the seed layer everywhere except under the coil itself. The present invention achieves this through etching in a solution of ammonium persulfate to which has been added the complexing agent 1,4,8,11 tetraazundecane. This suppresses the reduction of Cu++ to Cu, thereby increasing the dissolution rate of copper while decreasing that of nickel-iron. Two ways of implementing this are described—adding the complexing agent directly to the ammonium persulfate and introducing the 1,4,8,11 tetraazundecane through a dipping process that precedes conventional etching in the ammonium persulfate.

Abstract: An apparatus for electroplating a metal overlay on a substrate having a seed layer deposited on all surfaces. The apparatus includes a cell for containing and circulating an electrolyte and an annular sealing fixture having a “J” shaped cross section for supporting a peripheral front surface of the substrate. A multiplicity of compliant electrode fingers are inwardly mounted with a downward tilt angle. The compliant fingers make conductive cathodic contact with the seed layer at the peripheral edge of the substrate. A pressure is applied to the back surface of the substrate effecting a wiping action between the compliant fingers and the peripheral edge. A counter electrode is placed towards the bottom of the cell and is circuitous arranged for passing current between the counter electrode and compliant electrode fingers. A pump circulates the electrolyte against the front surface of the substrate.

Abstract: A chip package for semiconductor chips is provided by the method of forming a chip package includes the steps of forming a printed circuit board with a window therethrough; forming semiconductor chip connections of one or more primary chips which overlie the window to the printed circuit board by solder connections, locating a suspended semiconductor chip within the window, and connecting the suspended semiconductor chip to one or more primary chips overlying the window in a chip-on-chip connection. A bypass capacitor is formed on the printed circuit board.

Abstract: A new method is provided for the repair of a Phase Shifter Mask. The phase shifter of the PSM has been created over the active surface of the mask as a pattern of phase shift material, the pattern of phase shift material comprises at least one faulty element. A layer of photoresist is deposited over the active surface of the mask. A backside exposure of the PSM is performed in order to define the pattern of the mask in the layer of photoresist. The layer of photoresist is developed and remains in place over the pattern of the mask, protecting the phase shifter of the mask during repairs of the PSM. Repairs of the mask are performed using Focused Ion Beam techniques for this repair. A plasma etch removes Ga stain from the surface of the quartz substrate. The developed layer of photoresist is then removed from the pattern of the PSM using a wet strip process.