Abstract: A new method is provided for the repair of a Phase Shifter Mask. The phase shifter of the PSM has been created over the active surface of the mask as a pattern of phase shift material, the pattern of phase shift material comprises at least one faulty element. A layer of photoresist is deposited over the active surface of the mask. A backside exposure of the PSM is performed in order to define the pattern of the mask in the layer of photoresist. The layer of photoresist is developed and remains in place over the pattern of the mask, protecting the phase shifter of the mask during repairs of the PSM. Repairs of the mask are performed using Focused Ion Beam techniques for this repair. A plasma etch removes Ga stain from the surface of the quartz substrate. The developed layer of photoresist is then removed from the pattern of the PSM using a wet strip process.

Abstract: A new method of detecting a reticle option layer in an integrated circuit device has been achieved. The method may be applied to detect the presence of the threshold voltage implantation reticle option layer by direct die probing or by probing a pin of a package integrated circuit. The current through a first MOS transistor is measured by forcing a test voltage on the drain and the gate. The gate and the drain of the first MOS transistor are connected together while the source is connected to a reference voltage. The first MOS transistor has the standard threshold implantation but not the threshold voltage reticle option. The current through a second MOS transistor is measured by forcing the same test voltage on the drain and the gate. The gate and said drain of the second MOS transistor are connected together while the source is connected to a reference voltage. The second MOS transistor has the standard threshold voltage implantation and the threshold voltage implantation reticle option layer.

Abstract: It is often desirable to be able to perform an array of micro-chemical reactions simultaneously but with each reaction proceeding at a different temperature and/or for a different time. A classic example is the polymerase chain reaction associated with DNA analysis. In the present invention, this is achieved by means of an apparatus made up of a chip of plastic, or similar low cost material, containing an array of reaction chambers. After all chambers have been filled with reagents, the chip is pressed up against a substrate, typically a printed circuit board, there being a set of temperature balancing blocks between the chip and the substrate. Individually controlled heaters and sensors located between the blocks and the substrate allow each chamber to follow its own individual thermal protocol while being well thermally isolated from all other chambers and the substrate. The latter rests on a large heat sink to avoid temperature drift over time. A process for manufacturing the apparatus is also disclosed.

Abstract: The present invention is a serial to parallel data conversion method and device where new serial data are stored within a first n-bit register prior to presentation at an n-bit parallel output. Subsequently, additional data are stored within a second n-bit register while the data stored within the first register are presented at the parallel output. Data storage and data presentation are thereafter alternated, thereby eliminating the problem of setup time seen in prior art.

Abstract: Although MIM (metal injection molding) has received widespread application, aluminum has not been widely used for MIM in the prior art because of the tough oxide layer that grows on aluminum particles, thus preventing metal—metal bonding between the particles. The present invention solves this problem by adding a small amount of material that forms a eutectic mixture with aluminum oxide, and therefore aids sintering, to reduce the oxide, thereby allowing intimate contact between aluminum surfaces. The process includes the ability to mold and then sinter the feedstock into the form of compacted items of intricate shapes, small sizes (if needed), and densities of about 95% of bulk.

Abstract: A new electrostatic discharge protection device is achieved. A p-well region is in a semiconductor substrate. An n+ region in the p-well region is connected to a first voltage supply. An n-well region in the p-well region is spaced from the n+ region such that a depletion region will extend therebetween during normal operation. A p+ region in the n-well region is connected to a second voltage supply of greater value than the first voltage supply during normal operation. Current is conducted through the n+ region to the p+ region during an electrostatic discharge event.

Abstract: As track density requirements for disk drives have grown more aggressive, GMR devices have been pushed to narrower track widths to match the track pitch of the drive width. Narrower track widths degrade stability, cause amplitude loss, due to the field originating from the hard bias structure, and side reading. This problem has been overcome in a process of manufacturing a device by adding an additional layer of soft magnetic material above the hard bias layers. The added layer provides flux closure to the hard bias layers thereby preventing flux leakage into the gap region. A non-magnetic layer must be included to prevent exchange coupling to the hard bias layers. In at least one embodiment the conductive leads are used to accomplish this.

Abstract: A new method and structure is provided for the creation of a semiconductor inductor. Under the first embodiment of the invention, a semiconductor substrate is provided with a scribe line in a passive surface region and active circuits surrounding the passive region. At least one bond pad is created on the passive surface of the substrate close to and on each side of the scribe line. A layer of insulation is deposited, a layer of dielectric is deposited over the layer of insulation, at least one bond pad is provided on the surface of the layer of dielectric on each side of the scribe line. At least one inductor is created on each side of the scribe line on the surface of the layer of dielectric. A layer of passivation is deposited over the layer of dielectric. The substrate is attached to a glass panel by interfacing the surface of the layer of passivation with the glass panel. The substrate is sawed from the backside of the substrate in alignment with the scribe line.

Abstract: A new method is provided of treating the wafer prior to the process of singulating the wafer into individual die. A surface of the wafer over which CMOS image sensor devices have been created is coated with a layer of material that is non-soluble in water. The wafer is singulated by sawing through the layer of material that has been coated over the surface of the wafer and by then sawing through the wafer. The singulated die is then further processed by applying steps of die mount, wire bonding, surrounding the die in a mold compound and marking the package.

Abstract: A new digital follower device is achieved. The digital follower device comprises an n-channel vertical FET device and a p-channel vertical FET device. Each vertical FET device comprises a bulk region in a semiconductor substrate. The bulk region comprises a first doping type. A STI region is in the bulk region. A drain region is on a first side of the STI region. The drain region overlies the bulk region. The drain region comprises the first doping type. A gate region is on a second side of the STI region. The gate region comprises the first doping type. A voltage on the gate region controls a vertical channel in the bulk region. A buried region is between the gate region and the bulk region. The buried region comprises a second doping type. The n-channel FET device drain and the p-channel FET device drain are connected together. The n-channel FET device, gate and the p-channel FET device gate are connected together.

Abstract: An improved buried strap method in the fabrication of a DRAM integrated circuit device is described. A deep trench is etched into a substrate. A collar is formed on an upper portion of the deep trench. A buried plate is formed by doping around a lower portion of the deep trench and a capacitor dielectric layer is formed within the deep trench. The deep trench is filled with a silicon layer wherein the silicon layer forms a deep trench capacitor and covers the collar. The silicon layer is recessed below a top surface of the substrate to leave a recess. A top portion of the collar is etched away to leave a collar divot. A hemispherical grain polysilicon layer is selectively deposited into the deep trench and filling the collar divot. The HSG layer is doped in-situ or by post plasma doping. The doped hemispherical grain polysilicon layer forms a buried strap in the fabrication of a deep trench DRAM integrated circuit device.

Abstract: A new method of fabricating solder bumps in the manufacture of an integrated circuit device has been achieved. Contact pads are provided overlying a semiconductor substrate. A passivation layer is provided overlying the contact pads. The passivation layer has openings that expose a top surface of the contact pads. A sacrificial layer is deposited overlying the passivation layer and the exposed top surface of the contact pads. The sacrificial layer is not wettable to solder. Under bump metallurgy (UBM) caps may be formed either by deposition and patterning of a UBM layer stack or by selective electroless deposition of a material such as nickel and gold. An aperture mask is formed overlying the sacrificial layer. The aperture mask has openings that expose a part of the sacrificial layer overlying the contact pads. A solder layer is printed into the openings in the aperture mask. The solder layer is reflowed to form solder bumps overlying the contact pads. The aperture mask is stripped away.

Abstract: A method for compensating for the pulse area error of a Class-D power amplifier is achieved; especially it compensates the variations in the supply voltage and similar dependencies. A Class-D Amplifier typically gets pulse coded digital input (PCM) and may comprise a Sigma Delta Modulator to generate the signals driving the power output stage, typically an H-Bridge. A fundamental idea of this invention is to measure the real area of the output pulses, where the area is defined as the pulse duration multiplied by the pulse voltage amplitude, and to compare it with the ideal nominal pulse area. The pulse area error is calculated and then subtracted from said amplifier's input data. Key element of this invention is the “Pulse Area Compensation Function”, which calculates said real pulse area (voltage amplitude multiplied by time), compares said real pulse area with said ideal pulse area and feeds the difference into the input of said Sigma Delta Modulator.

Abstract: A method for integrating low-K materials in semiconductor fabrication. The process begins by providing a semiconductor structure having a dielectric layer thereover, wherein the dielectric layer comprising an organic low-K material. The dielectric layer is patterned to form pillar openings. A pillar layer is deposited over the semiconductor structure; thereby filling the pillar openings with the pillar layer. The pillar layer is planarized to form pillars embedded in said dielectric layer. The pillar layer comprises a material having good thermal stability, good structural strength, and good bondability of spin coating back-end materials, improving the manufacturability of organic, low-K dielectrics in semiconductor fabrication. In one embodiment, the pillars are formed prior to forming dual damascene interlayer contacts. In another embodiment, pillars are formed simultaneously with interlayer contacts.

Abstract: A method of forming multiple gate oxide thicknesses on active areas that are separated by STI isolation regions on a substrate. A first layer of oxide is grown to a thickness of about 50 Angstroms and selected regions are then removed. A second layer of oxide is grown that is thinner than first growth oxide. For three different gate oxide thicknesses, selected second oxide growth regions are nitridated with a N2 plasma which increases the dielectric constant of a gate oxide and reduces the effective oxide thickness. To achieve four different gate oxide thicknesses, nitridation is performed on selected first growth oxides and on selected second growth oxide regions. Nitridation of gate oxides also prevents impurity dopants from migrating across the gate oxide layer and reduces leakage of standby current. The method also reduces corner loss of STI regions caused by HF etchant.

Abstract: In this invention, by offering specific array-end structures and their fabrication method, the three resistive layers of diffusion bit line, control gate and word gate polysilicons, where control gate polysilicon can run on top of the diffusion bit line, are most effectively stitched with only three layers of metal lines keeping minimum metal pitches. The stitching method can also incorporate a bit diffusion select transistor and/or a control gate line select transistor. The purpose of the select transistors may be to reduce the overall capacitance of the bit line or control gate line, or to limit the disturb conditions that a grouped sub-array of cells may be subjected to during program and/or erase.

Abstract: It is important for a CPP GMR read head that it have both high resistance as well as high cross-sectional area. This has been achieved by inserting a NOL (nano-oxide layer) though the middle of one or both of the two non-magnetic conductive layers. A key feature is that the NOL is formed by first depositing the conductive layer to about half its normal thickness. Then a metallic film is deposited thereon to a thickness that is low enough for it to still consist of individual islands. The latter are then fully oxidized without significantly oxidizing the conductive layer on which they lie. The remainder of the conductive layer is then deposited to a thickness sufficient to fully enclose the islands of oxide.

Abstract: The present invention describes a two transistor flash EEPROM memory cell which has a symmetrical source and drain structure, which permits the cell size not limited by program and erase operations. The memory cell comprises an NMOS floating gate transistor forming a nonvolatile storage device and an NMOS transistor forming an access device. The floating gate transistor is programmed and erased using Fowler-Nordheim channel tunneling. The two transistor memory cell is used in a memory array of columns and rows where a column of cells is coupled by a bit line and a source line, and where a row of cells is coupled by a word line and an access line. The memory array is highly scalable and is targeted for low-voltage, high-speed and high-density programmable logic devices.

Abstract: The invention proposes to simplify fabrication of the twin MONOS memory array. The twin MONOS memory array can be embedded into a standard CMOS circuit by the process of the present invention by adding only three additional mask levels. Conventional floating gate devices need ten or more extra masks. In the present invention, the unique twin MONOS process steps can be inserted into the standard CMOS process flow without any parameter modifications. The present invention also achieves increased endurance by means of reducing the widths of the sidewall control gate and underlying nitride storage region.

Abstract: A new method is provided for the creation of a solder bump. Conventional methods are initially followed, creating a patterned layer of Under Bump Metal over the surface of a contact pad. A layer of photoresist is next deposited, this layer of photoresist is patterned and developed creating a resist mask having a T-shape opening aligned with the contact pad. This T-shaped opening is filled with a solder compound, creating a T-shaped layer of solder compound on the surface of the layer of UBM. The layer of photoresist is removed, exposing the Created T-shaped layer of solder compound, further exposing the layer of UBM. The layer of UBM is etched using the T-shaped layer of solder compound as a mask. Reflow of the solder compound results in creating a solder ball.