Abstract: A method of forming an electrical metal fuse comprising the following steps. A substrate is provided. A first patterned dielectric layer is formed over the substrate. The first patterned dielectric layer having at least one first opening exposing at least a portion of the substrate. A first planarized structure is formed within the at least one first opening. A second patterned dielectric layer is formed over the first planarized structure. The second patterned dielectric layer having a second opening exposing at least a portion of the first planarized structure. A second planarized structure is formed within the second opening whereby the first planarized structure and the second planarized structure comprise the electrical metal fuse. The electrical metal fuse having a middle portion, having a thickness and a width, between two end portions each having a thickness and a width. The thickness and width of the middle portion being less than the respective thickness and width of the end portions.

Abstract: A method of driving-in antimony into a wafer, including the following steps. A wafer is loaded into an annealing furnace/tool. The wafer having an area of implanted antimony ions. The wafer is annealed a first time at a first temperature in the presence of only a first nitrogen gas flow rate. The wafer is ramped-down from the first temperature to a second temperature in the presence of only an oxygen gas flow rate. The wafer is maintained in the presence of the of oxygen gas flow rate at the second temperature. The wafer is ramped-up from the second temperature to a third temperature in the presence of only the oxygen gas flow rate. The wafer is annealed a second time at the third temperature in the presence of only a second nitrogen gas flow rate to drive-in the antimony ions within the area of implanted antimony.

Abstract: A first low-k layer is formed over a structure having an exposed active device. A patterned first nitride layer having an opening therethrough aligned over a portion of the active device is formed. Nitride spacers are formed over the side walls of the opening. A second low-k layer is formed over the patterned first nitride layer, filling the patterned first nitride layer opening. The second low-k layer and the first low-k layer through the opening reduced by the nitride spacers are patterned to expose a portion of the active device to form a preliminary dual damascene. The nitride spacers and the first nitride layer exposed by the preliminary dual damascene opening are removed to form a final upper horizontal interconnect opening having substantially 90° edges. The first and second low-k layers are then reflowed to round the substantially 90° edges of the first and second low-k layer.

Abstract: A method of forming a shallow trench isolation structure comprising the following steps. A substrate having an upper surface is provided. A pad oxide layer is formed upon the substrate. A nitride layer is formed over the pad oxide layer. The nitride layer having an upper surface. A trench is formed by etching the nitride layer, pad oxide layer and a portion of the substrate. The trench having a bottom and side walls. An oxide film is deposited upon the etched nitride layer surface, and the bottom and side walls of trench. The oxide film is removed from over the etched nitride layer surface, and the bottom of the trench to expose a portion of substrate within the trench. The removal of oxide film leaving oxide spacers over the trench side walls. Epitaxial silicon is selectively deposited over the exposed portion of substrate, filling the trench. A thermal oxide layer is formed over the epitaxial silicon, annealing the interface between the epitaxial silicon and the oxide spacers.

Abstract: A method of forming a borderless contact, comprising the following steps. A substrate having an exposed conductive structure is provided. An oxynitride etch stop layer is formed over the substrate and the exposed conductive structure. An oxide dielectric layer is formed over the oxynitride etch stop layer. The oxide dielectric layer is etched with an etch process having a high selectivity of oxide-to-oxynitride to form a contact hole therein exposing a portion of the oxynitride etch stop layer over at least a portion of the exposed conductive structure. The etch process not appreciably etching the oxynitride etch stop layer and including: a fluorine containing gas; an inert gas; and a weak oxidant. The exposed portion of the oxynitride etch stop layer over at least a portion of the conductive structure is removed. A borderless contact is formed within the contact hole. The borderless contact being in electrical connection with at least a portion of the conductive structure.

Abstract: A fusible link device and a method of making same. The fusible link device comprising a poly layer having a center undoped portion and two doped end portions. The center undoped portion having a first resistance and the two doped end portions each having a second resistance that is lower than the first resistance. A silicide layer is formed over the poly layer with the silicide layer having a third resistance lower than the second resistance. The silicide layer agglomerating to form an electrical discontinuity within a discontinuity area in response to a predetermined programming potential being applied across the silicide layer, such that the resistance of the fusible link device can be selectively increased. The agglomeration of the silicide layer occurring over the center undoped portion of the poly layer. Contacts are electrically coupled to the two doped poly layer end portions for receiving the programming potential.

Abstract: A method of fabricating a die-up laminated PBGA package, including the following steps. A mold chase for a PBGA package is provided. The mold chase has an open side with and exposed bottom wall and side walls, and a bottom side. The mold chase is positioned open side up. A heat spreader is dropped into the mold chase open side. The heat spreader has a lower protruding section, and lateral peripheral flanges with gaps therebetween. The protruding section contacts a portion of the bottom wall of the mold chase and the flanges contact a portion of the exposed side walls of the mold chase to thereby secure the heat spreader within the mold chase. A substrate, having a die affixed thereto in a die down position, is fixedly placed over the mold chase. The die being positioned within the space above the protruding section of the heat spreader.

Abstract: A method of forming a gate comprising the following steps. A substrate is provided. A pre-gate structure is formed over the substrate. The pregate structure includes a sacrificial metal layer between an upper gate conductor layer and a lower gate dielectric layer. The pre-gate structure is annealed to form the gate. The gate comprising: an upper silicide layer formed from a portion of the sacrificial metal layer and a portion of the upper gate conductor layer from the anneal; and a lower metal oxide layer formed from a portion of the gate dielectric layer and a portion of the sacrificial metal layer from the anneal.

Abstract: A method of fabricating a metal-oxide-metal (MOM) capacitor, comprising the following steps. A bottom metal layer is deposited. A high dielectric constant oxide insulator is deposited layer over the bottom metal layer. The structure is annealed in an oxidizing ambient to cause the exposed bottom metal to form a metal oxide partially filling the one or more pin hole defects to repair those pin hole defects. An upper oxide conductor layer is then deposited over the high dielectric constant oxide insulator layer. An upper metal layer is deposited over said upper oxide conductor layer.

Abstract: A method of forming interconnect structures in a semiconductor device, comprising the following steps. A semiconductor structure is provided. In the first embodiment, at least one metal line is formed over the semiconductor structure. A silicon-rich carbide barrier layer is formed over the metal line and semiconductor structure. Finally, a dielectric layer, that may be fluorinated, is formed over the silicon-rich carbide layer. In the second embodiment, at least one fluorinated dielectric layer, that may be fluorinated, is formed over the semiconductor structure. The dielectric layer is patterned to form an opening therein. A silicon-rich carbide barrier layer is formed within the opening. A metallization layer is deposited over the structure, filling the silicon-rich carbide barrier layer lined opening. Finally, the metallization layer may be planarized to form a planarized metal structure within the silicon-rich carbide barrier layer lined opening.

Abstract: A method of preventing metal penetration and diffusion from metal structures formed over a semiconductor structure, comprising the following steps. A semiconductor structure including a patterned dielectric layer is provided. The patterned dielectric layer includes an opening and an upper surface. The dielectric layer surface is then passivated to form a passivation layer. A metal plug is formed within the dielectric layer opening. The passivation layer prevents penetration and diffusion of metal out from the metal plug into the semiconductor structure and the patterned dielectric layer.

Abstract: A method for filling a trench within a silicon substrate. There is first provided a silicon substrate having a trench formed therein. There is then formed upon the substrate and within the trench a gap filling silicon oxide trench fill layer employing an ozone assisted thermal chemical vapor deposition (SACVD) method. There is then carried out a densification of the gap filling silicon oxide trench fill layer by annealing in an oxidizing atmosphere at an elevated temperature. Finally, the gap filling silicon oxide trench fill layer is planarized by chemical mechanical polish (CMP) planarization to form the silicon oxide trench filling layer with attenuated surface sensitivity and with an enhanced bulk quality and reduced trench recess at corners.

Abstract: A method of bonding a bonding element to a metal bonding pad, comprising the following steps. A semiconductor structure having an exposed metal bonding pad within a passivation layer opening is provided. The bonding pad has an upper surface. A bonding element is positioned to contact the bonding pad upper surface. A bonding solution is applied within the passivation layer opening, covering the bonding pad and a portion of the bonding element. The structure is annealed by heating said bonding element to selectively solidify the bonding solution proximate said contact of said bonding element to said bonding pad, bonding the bonding element to the bonding pad.

Abstract: A method of forming a conductive cap layer over a metal bonding pad comprises the following steps. A semiconductor structure is provided having an exposed, recessed metal bonding pad within a layer opening. The layer has an upper surface. The exposed metal bonding pad is treated with a solution containing soluble metal ions to form a conductive cap over the metal bonding pad. The conductive cap layer is comprised of the solution metal and has a predetermined thickness. An external bonding element may then be bonded to the conductive cap, forming an electrical connection with the metal bonding pad.

Abstract: A method of forming a non-oxidized WSix layer on a semiconductor wafer, including the following steps. A semiconductor wafer having a silicon substrate is provided within a CVD tool. A WSix layer is formed over the silicon substrate. An SiN layer is formed upon the WSix layer in absence of O2; whereby the WSix layer is non-oxidized.

Abstract: A method of forming a high transmittance attenuated phase-shifting mask, comprising the following steps. A patterned shifter blank including a patterned shifter layer, having a first variable transmittance and a first phase angle overlying a partially exposed transparent substrate is provided. The partially exposed transparent substrate is etched for a first predetermined time to form trenches therein having a predetermined depth, increasing the first variable transmittance and the first phase angle to a second variable transmittance and a second phase angle, respectively. The shifter layer is treated with an aqueous solution of NH4OH:H2O2 for a second predetermined time, increasing the second variable transmittance to a third and final, predetermined variable transmittance, and decreasing the second phase angle to a third phase angle. Whereby the third phase angle is substantially equal to the initial phase angle of said shifter layer.

Abstract: A method for forming a patterned silicon containing layer. There is first provided a substrate. There is then formed over the substrate a blanket silicon containing layer. There is then formed over the blanket silicon containing layer a patterned photoresist layer. There is then etched, while employing a first plasma etch method in conjunction with the patterned photoresist layer as a first etch mask layer, the blanket silicon containing layer to form a partially etched blanket silicon containing layer. The first plasma etch method employs a first etchant gas composition comprising an etchant gas which upon plasma activation forms an active fluorine containing etchant species. There is then etched, while employing a second plasma etch method in conjunction with the patterned photoresist layer as a second etch mask layer the partially etched blanket silicon containing layer to form a fully patterned silicon containing layer.

Abstract: Formation of integrated color filters for gain-ratio balanced semiconductor array imagers using a spectrophotometric feedback control loop to adjust layer thickness during the deposition process is disclosed. The fabrication sequence of G/R/B conventionally used in Prior Art has been changed to B/R/G or B/G/R to enable the process to adapt to yielding specified color gain-ratio values without the need for integrated circuit redesign. A high efficiency color filter process is demonstrated wherein the additional neutral-density attenuator layers and/or spacer layers required in Prior Art fabrication methods are eliminated. The disclosed process is shown to enable high-precision thickness control of the color filter layers. Blue coating lift-off problems and the steric effect associated with successive depositions of color layers having step-height variations are eliminated.

Abstract: A method of forming a metal plug, comprising the following steps. An etched dielectric layer, over a conductive layer, over a semiconductor structure are provided. The etched dielectric layer having a via hole and an exposed periphery. The etched dielectric layer is treated with at least one alkaline earth element source to form an in-situ metal barrier layer within the dielectric layer exposed periphery. A metal plug is formed within the via hole wherein the in-situ metal barrier layer prevents diffusion of the metal from the metal plug into the dielectric oxide layer.

Abstract: A cleaner composition for removing from within a microelectronic fabrication a copper containing residue layer in the presence of a copper containing conductor layer, and a method for stripping from within a microelectronic fabrication the copper containing residue layer in the presence of the copper containing conductor layer. The cleaner composition comprises: (1) a hydroxyl amine material; (2) an ammonium fluoride material; and (3) a benzotriazole (BTA) material. The cleaner composition contemplates the method for stripping from within the microelectronic fabrication the copper containing residue layer in the presence of the copper containing conductor layer.