Abstract: A method for forming a dielectric layer. There is first provided a substrate. There is then formed over the substrate a patterned conductor layer. There is then formed upon the patterned conductor layer, while employing a plasma enhanced chemical vapor deposition (PECVD) method, a silicon containing dielectric layer, wherein when forming the silicon containing dielectric layer there is controlled a temperature of the substrate so that there is enhanced a line-to-line capacitance uniformity of the patterned conductor layer.

Abstract: A semiconductor chip having an exposed metal terminating pad thereover, and a separate substrate having a corresponding exposed metal track thereover are provided. A metal bump is formed over the exposed metal terminating pad. A photosensitive resin plug is formed over the metal bump. The metal bump of the semiconductor chip is aligned with the corresponding metal track on the separate substrate. The photosensitive resin plug over the metal bump is mated with the corresponding the metal track. The photosensitive resin plug is exposed to UV light to cure the photosensitive resin plug, permanently attaching the metal bump of the semiconductor chip to the corresponding metal track of the separate substrate.

Abstract: A method of forming via plugs in a semiconductor device, comprising the following steps. A semiconductor structure having an upper first oxide layer and at least two metal lines formed on the upper oxide layer are provided. The metal lines are spaced apart a predetermined distance and each having a lower barrier layer, a middle layer, and an upper etch stop layer. A second oxide layer is deposited over the first oxide layer and the pair of metal lines. An etch barrier layer is formed over the second oxide layer. The structure is planarized to form openings in the etch barrier layer over the metal lines. A third oxide layer is deposited and patterned over the planarized structure to form via openings through the etch barrier layer openings to the upper etch stop layers on the metal lines. Metal via plugs are formed in the via openings.

Abstract: A method for forming through a dielectric layer a trench contiguous with a via. There is first provided a substrate having a contact region formed therein. There is then formed upon the substrate a blanket first dielectric layer. There is then formed upon the blanket first dielectric layer a blanket etch stop layer. There is then formed upon the blanket etch stop layer a patterned first photoresist layer which defines a location of a via to be formed through the blanket etch stop layer and the blanket first dielectric layer to access the contact region. There is then etched while employing a first etch method the blanket etch stop layer to form a patterned etch stop layer.

Abstract: A method for forming a patterned reflective layer first employs a substrate. There is then formed over the substrate a blanket reflective layer. There is then formed upon the blanket reflective layer an anti-reflective coating (ARC) layer formed employing a plasma enhanced chemical vapor deposition (PECVD) method employing a deposition gas composition comprising silane, nitrous oxide and argon. There is then formed upon the blanket anti-reflective coating (ARC) layer a blanket photoresist layer. There is then photoexposed and developed the blanket photoresist layer to form a patterned photoresist layer. There is then etched, while employing a first etch method, the blanket anti-reflective coating (ARC) layer to form a patterned anti-reflective coating (ARC) layer while employing the patterned photoresist layer as a first etch mask layer.

Abstract: A buffer layer and a gate dielectric layer overlying a substrate having at least one active area is provided. A sacrificial oxide layer is formed over the gate dielectric layer. A nitride layer is formed over the sacrificial oxide layer. The nitride layer is patterned to form an opening therein within the active area exposing a portion of the sacrificial oxide layer within the opening. The portion of the sacrificial oxide layer within the opening is stripped, exposing a portion of the underlying gate dielectric layer within the opening. A gate electrode is formed within opening over the portion of the gate dielectric layer. The remaining nitride layer is selectively removed. The remaining sacrificial oxide layer is then stripped and removed.

Abstract: A plasma etch method for forming a patterned layer first employs a substrate having formed therover a blanket microelectronic layer. There is also formed over the blanket microelectronic layer a patterned mask layer. There is then etched, while employing a first plasma etch method which employs the patterned mask layer as an etch mask layer, the blanket microelectronic layer to form a partially etched blanket microelectronic layer. There is then etched, while employing a second plasma etch method which employs the patterned mask layer as an etch mask layer, the partially etched blanket microelectronic layer to form a patterned microelectronic layer. Within the present invention, the first plasma etch method employs a higher bias voltage than the second plasma etch method.

Abstract: A method of forming a gate electrode, comprising the following steps. A semiconductor substrate having an overlying patterned layer exposing a portion of the substrate within active area and patterned layer opening. The patterned layer having exposed sidewalls. Internal spacers are formed over a portion of the exposed substrate portion within the patterned layer opening on the patterned layer exposed sidewalls. The internal spacers being comprised of a WF1 material having a first work function. A planarized gate electrode body is formed within the remaining portion of the patterned layer opening and adjacent to the internal spacers. The gate electrode body being comprised of a WF2 material having a second work function. The internal spacers and the gate electrode body forming the gate electrode.

Abstract: A method of fabricating an SOI transistor device comprises the following steps. a silicon semiconductor structure is provided. A silicon oxide layer is formed over the silicon semiconductor structure. A silicon-on-insulator layer is formed over the oxide layer. A well is implanted in the silicon-on-insulator layer. A gate oxide layer is grown over the silicon-on-insulator layer. A polysilicon layer is deposited over the gate oxide layer. The polysilicon layer, gate oxide layer, and silicon oxide layer are patterned and etched to form trenches. The trenches are filled with an isolation material to at least a level even with a top surface of the polysilicon layer to form raised shallow trench isolation regions (STIs). The polysilicon layer is patterned and the non-gate portions are removed polysilicon adjacent the raised STIs forming a gate conductor between the raised STIs with the gate conductor and said raised STIs having exposed sidewalls.

Abstract: A method of fabricating a floating gate/word line device, comprising the following steps. A semiconductor structure is provided. A floating gate portion is formed over the semiconductor structure. The floating gate portion having side walls and a top surface. A poly-oxide portion is formed over the top surface of the floating gate. An interpoly oxide layer is formed over the semiconductor structure, the poly-oxide portion and the poly-oxide portion. The interpoly oxide layer having an initial thickness and includes: a word line region portion over at least a portion of the semiconductor structure adjacent the floating gate portion; side wall area portions over the floating gate portion side walls; and a top portion over the poly-oxide portion. The initial thickness of the top portion of the interpoly oxide layer is reduced to a second thickness without reducing the initial thickness of the interpoly oxide word line region portion or an appreciable portion of the interpoly oxide side wall area portion.

Abstract: A method for forming a via through a dielectric layer within a microelectronics fabrication. There is first provided a substrate employed within a microelectronics fabrication. There is then formed over the substrate a silicon oxide dielectric layer, where the silicon oxide dielectric layer is formed through use of a plasma enhanced chemical vapor deposition (PECVD) method employing tetra-ethyl-ortho-silicate (TEOS) as a silicon source material. There is then treated the silicon oxide dielectric layer with a plasma to form a plasma treated silicon oxide dielectric layer. Finally, there is then formed upon the plasma treated silicon oxide dielectric layer a patterned photoresist layer employed in defining the location of a via to be formed through the plasma treated silicon oxide dielectric layer.

Abstract: A method for forming through a dielectric layer a trench contiguous with a via. There is provided a substrate having a contact region formed therein. There is then formed upon the substrate a patterned first dielectric layer defining a via accessing the contact region, where the patterned first dielectric layer is formed of a first dielectric material which is not susceptible to etching with an oxygen containing plasma. There is then formed completely covering the patterned first dielectric layer and filling the via a the blanket second dielectric layer formed of a second dielectric material which is susceptible to etching within the oxygen containing plasma. There is then formed upon the blanket second dielectric layer a blanket hard mask layer formed from a hard mask material which is not susceptible to etching within the oxygen containing plasma.

Abstract: A method of forming a metal interconnect within a fluorinated silica glass dielectric layer while preventing outgassing from the FSG dielectric layer, comprising the following steps. A semiconductor structure having a metal structure, with an overlying liner layer, formed thereover is provided. A FSG dielectric layer is formed over the liner layer. The FSG dielectric layer having an exposed upper surface. The FSG dielectric layer is treated with a first nitrogen gas/plasma treatment to form a fluorine depleted upper capping layer from the exposed surface of the FSG dielectric layer. A TEOS oxide layer is formed over the upper capping layer. The TEOS oxide layer is planarized to form a planarized TEOS oxide layer. The planarized TEOS oxide layer, the upper capping layer, the treated FSG dielectric layer, and the liner layer are patterned to form a via hole therethrough, exposing a portion of the metal structure and exposing sidewalls of the patterned treated FSG dielectric layer within the via opening.

Abstract: A method for forming a microelectronic layer. There is first provided a substrate. There is then formed over the substrate the microelectronic layer while employing a plasma enhanced chemical vapor deposition (PECVD) method employing a source material gas and a carrier gas, wherein there is employed a sufficiently low plasma power, a sufficiently low source material gas:carrier gas flow rate ratio and a sufficiently high carrier gas atomic mass such that the microelectronic layer is formed with enhanced film thickness uniformity. The method may be employed for forming ion implant screen layers, such as silicon oxide ion implant screen layers, with enhanced film thickness uniformity.

Abstract: A method for forming a patterned hard mask layer. There is first provided a substrate. There is then formed over the substrate a blanket hard mask layer formed of a hard mask material susceptible to etching within a first plasma etch method, where the first plasma etch method employs a first etchant gas composition which upon plasma activation forms an active fluorine containing etchant species. There is then formed over the blanket hard mask layer a patterned photoresist layer. There is then etched, while employing the first plasma etch method in conjunction with the patterned photoresist layer as a first etch mask layer, the blanket hard mask layer to form a patterned hard mask layer which defines a first aperture. The first plasma etch method also forms at the bottom of the first aperture defined by the patterned hard mask layer a residue. Finally, there is then etched, while employing a second etch method, the residue from the bottom of the first aperture.

Abstract: A chemical mechanical polish (CMP) planarizing method for forming a chemical mechanical polish (CMP) planarized microelectronic layer within a microelectronic fabrication employs first a substrate. There is then formed over the substrate a microelectronic layer. There is then planarized, while employing a chemical mechanical polish (CMP) planarizing method, the microelectronic layer to form a chemical mechanical polish (CMP) planarized microelectronic layer. Within the method, the microelectronic layer when formed over the substrate is formed with a thickness variation which compensates for a chemical mechanical polish (CM) rate non-uniformity when forming while employing the chemical mechanical polish (CMP) planarizing method the chemical mechanical polish (CMP) planarized microelectronic layer from the microelectronic layer.

Abstract: A clamp for fixturing a substrate when forming and thermal processing upon the substrate a thermally flowable layer. The clamp is formed from a backing member connected to a top member through a mechanical means. The backing member and the top member are sized such that a substrate may be clamped between the backing member and the top member. A portion of the top member overlaps the substrate and leaves exposed a first portion of the substrate when the substrate is clamped between the backing member and the top member. The top member has a cross-sectional profile such that a thermally flowable layer residue formed upon the top member when a thermally flowable layer is formed upon the substrate will not flow from the top member and bridge to the thermally flowable layer when the thermally flowable layer is thermally processed.

Abstract: A method for forming an antifuse interconnect structure, for a one-time fusible link, to be used with field-programmable gate arrays, has been developed. The process features the use of an amorphous silicon layer, used as the antifuse layer, with the amorphous silicon layer protected by a thin barrier layer, during the patterning procedure. The protected antifuse layer results in a reproducible thickness, and thus reproducible pulsing voltages, needed for rupturing of the antifuse layer. Planarization of an underlying metal plug, via a conductor layer refill procedure, offers a smooth top surface, flush with the top surface of the adjacent interlevel dielectric layer, for the overlying antifuse layer.

Abstract: A method for forming a dielectric layer upon a substrate within a microelectronics fabrication. There is provided a substrate. There is then formed upon the substrate while employing a low dielectric constant spin-on material a dielectric layer which is subsequently cured at atmospheric pressure at an elevated temperature to stabilize the physical and chemical properties of the low dielectric constant dielectric layer so as to attenuate shrinkage and other changes in those physical, and chemical properties from thermal annealing at sub-atmospheric pressure due to typical further microelectronics fabrication processing steps.

Abstract: A method for forming a metal silicide layer. There is first provided a substrate. There is then formed over the substrate a silicon layer, where the silicon layer has other than an amorphous silicon surface. There is then annealed thermally the silicon layer at a temperature greater than a silicidation temperature for forming a metal silicide layer upon the silicon layer to thus form from the silicon layer a thermally annealed silicon layer. Finally, there is then deposited upon the thermally annealed silicon layer a metal silicide forming metal while employing a metal deposition method such that upon contact with the thermally annealed silicon layer the metal silicide forming metal reacts in-situ to form a metal silicide layer upon a partially consumed thermally annealed silicon layer formed from the thermally annealed silicon layer.