Abstract: A converter apparatus and method are provided that transforms an external low speed industry standard interface into an on-chip high speed serial link (HSSL). The converter of the present invention is preferably placed in close vicinity of the external interface. The HSSL operates at the system clock speed and, as a result, the HSSL interface signals can be readily treated like any other timed signal facilitating the physical design process. Because synchronization is performed once in the converter near the external interface and the signals along the HSSL of the present invention may be treated like any other timed signal, the need for interface units in each processing element of the chip to perform synchronization is eliminated. Thus, the complexity and silicon area used by the present invention is reduced. The converter enables the maximum speed for the serial interface, which is crucial in power-on-reset, manufacturing testing, and chip debugging.

Abstract: Method and system for partitioning and delivery data using a delegation object is disclosed. The delegation object is a first-class object, and includes a master data set definition, a data dimension-to-user mapping and a target organization definition. The target organization definition defines relationships between the master data set definition and the data dimension-to-user mapping. The delegation object is used to create a specific data set from a master data set.

Abstract: A mechanism for using electrical fuses (eFuses) to store phase-locked loop (PLL) configuration data are provided. With the mechanism, a portion of the eFuses present in the integrated circuit are reserved for the PLL configuration data. Upon power up, a power up controller and eFuse controller direct the sensing and serial transfer of the data in the portion of eFuses to the PLL under the reference clock. When the transfer is complete, the power up controller directs the PLL logic to load the configuration data and start. The mechanism of the present invention allows manufacturing to tailor the PLL configuration on a given device based on the characteristics of that device and its intended usage. Thus, the same PLL may be used in the same or different architectures to perform different operations based on the configuration data passed into the PLL from the eFuses.

Abstract: A method for conversion between a decimal floating-point number and an order-preserving format has been disclosed. The method encodes numbers in the decimal floating-point format into a format which preserves value ordering. This encoding allows for fast and direct string comparison of two values. Such an encoding provides normalized representations for decimal floating-point numbers and supports type-insensitive comparisons. Type-insensitive comparisons are often used in database management systems, where the data type is not specified for values to compare. In addition, the original decimal floating-point format can be recovered from the order-preserving format.

Abstract: A system and method for correlated analysis of wasted space and capacity efficiency in complex storage infrastructures are provided. The system and method of the illustrative embodiments bring together wasted space data from all areas and components of the storage infrastructure into a single set of reports correlating information from these various sources in the storage infrastructure. In addition, correlated analysis of this collected information is performed with regard to wasted space. Logical storage devices of the storage infrastructure which are unused by host systems may be identified and appropriate corrective actions may be automatically taken. Moreover, automated recommendations and other automated corrective actions may be taken based upon the correlated analysis of the correlated data collected from the various components of the storage infrastructure.

Abstract: Mechanisms are disclosed that enable a user to customize selection elements of a GUI. For example, menu entries in a GUI can be customized so that the user can specify the font, the language, character sets, color, and other attributes of the text of one menu item (or less than all menu items); to have the ability to selectively activate multimedia options associated with selected menu items (e.g., to play a sound whenever the cursor/pointer passes over a particular menu item); and/or to assign an animation sequence that is unique to selected menu items. The menu item properties are defined by the user, using, for example, a dialog box that allows specification of the attributes. When the application is installed, a default set of menu item properties is defined by the software manufacturer, which can be further customized by the user.

Abstract: Mechanisms are disclosed that enable a user to customize selection elements of a GUI. For example, menu entries in a GUI can be customized so that the user can specify the font, the language, character sets, color, and other attributes of the text of one menu item (or less than all menu items); to have the ability to selectively activate multimedia options associated with selected menu items (e.g., to play a sound whenever the cursor/pointer passes over a particular menu item); and/or to assign an animation sequence that is unique to selected menu items. The menu item properties are defined by the user, using, for example, a dialog box that allows specification of the attributes. When the application is installed, a default set of menu item properties is defined by the software manufacturer, which can be further customized by the user.

Abstract: Mechanisms for balancing bus bandwidth across a plurality of PCI-Express (PCIe) endpoints are provided. Firmware automatically operates in concert with established data structures to set operational parameters of the PCIe endpoints so as to maximize usage of the available bandwidth of a front-side bus while minimizing isochronous issues and the likelihood that the performance of the PCIe endpoints cannot be guaranteed. A first table data structure comprises various combinations of operational parameter settings for controlling bandwidth usage of each of the endpoints of the data processing system. A second table data structure contains a listing of the endpoints that the data processing system supports with their associated minimum data rates, priorities, and whether the endpoints have isochronous requirements. A setting of the desired bandwidth balancing level is used along with these data structures to determine how to adjust the operating parameters of the PCIe endpoints.

Abstract: A conditioning buffer is provided for a clock interpolator that controls the duration of the clock edges to achieve high-linearity interpolation. The conditioning buffer includes a first buffer and a second buffer, with a fixed or variable strength, that receive their respective inputs from a set of mutually delayed clock signals, such as a set of N equidistant clock phases with mutual delay of 360/N degrees, to form a two-tap transversal filter that is insensitive to changes in Process, Temperature, and Voltage (PVT). Use of an equidistant set of clock phases makes the time constant of such transversal filter proportional to the clock period thus making it insensitive to changes in clock frequency as well. Such transversal filtering action operated in conjunction with natural bandwidth limitations of the buffers yields an efficient clock conditioning circuit that is highly insensitive to PVT and clock frequency variations.

Abstract: Mechanisms are provided for calculating a recovery time (tr) of an application system in a computer system. The mechanisms tune the computer system dynamically. A recovery time (tr) is calculated and controlled within flexible predefined time slices and compared to a predefined time period (t0). A trigger is set in the case in which the calculated recovery time (tr) exceeds the predefined time period (t0). The mechanisms determine a type of redolog used during a backup process and a corresponding recovery speed value associated with the type of redolog. The recovery time is calculated based on the type of redolog used during the backup process and the corresponding recovery speed value associated with the type of redolog.

Abstract: Mechanisms for migration stateless virtual functions from one virtual plane to another are provided. When a migration of a source virtual function to a destination virtual function in another virtual plane is to be performed, a source single root PCI manager (SR-PCIM) is first interrupted by a multiple root PCI manager (MR-PCIM). Configuration information that defines the source virtual function is then redefined on the destination virtual function for this stateless migration. A function level reset may then be performed on the source virtual function. The destination SR-PCIM may be interrupted by the MR-PCIM with an interrupt for the destination virtual function. A function level reset may then be performed on the destination virtual function. The destination virtual function state may then be changed to an “active” state such that the migrated virtual function begins processing transactions.

Abstract: A method for preventing time of check to time of use exploits includes receiving a system call from a user space at a system call intercept and copying user space parameters from the user space to a kernel space responsive to the system call. The method also includes copying the user space parameters from the kernel space to a secure location in the user space, receiving the user space parameters from the secure location at the system call intercept, and executing the system call based on the received user space parameters. A computer readable medium including computer readable code and a system for executing the method steps are also disclosed.

Abstract: A mechanism for priority control in resource allocation for low request rate, latency-sensitive units is provided. With this mechanism, when a unit makes a request to a token manager, the unit identifies the priority of its request as well as the resource which it desires to access and the unit's resource access group (RAG). This information is used to set a value of a storage device associated with the resource, priority, and RAG identified in the request. When the token manager generates and grants a token to the RAG, the token is in turn granted to a unit within the RAG based on a priority of the pending requests identified in the storage devices associated with the resource and RAG. Priority pointers are utilized to provide a round-robin fairness scheme between high and low priority requests within the RAG for the resource.

Abstract: Mechanisms for controlling a commercial transaction are presented. An article of manufacture has a time cell that is read by an electronic apparatus. In response to a determination of a state of the time cell by the electronic apparatus, usage of the article of manufacture in a commercial transaction is enabled or denied based on the determined state of the time cell. The expiration period of a time cell controls the time period during which the commercial transaction is enabled or is denied to be performed; an unexpired time cell may both enable or deny performance of a commercial transaction, and an expired time cell may also both enable or deny performance of a commercial transaction. The time cell may be used to restrict the usage period of a coupon, a promotional offer, a pre-paid service, or some other commercial transaction that involves an article of manufacture.

Abstract: An example of a solution provided here comprises automatically measuring bandwidth of a network connection; comparing results of the measuring, with bandwidth parameters; preventing a transfer of a file via the network connection, if measured bandwidth is less than a minimum acceptable value; providing to an end user an option of transferring a file via the network connection, if measured bandwidth is not less than a minimum acceptable value, but is less than an optimal value; and automatically transferring a file via the network connection, if measured bandwidth is greater than or equal to an optimal value.

Abstract: A method for providing a transient electronic dictionary that travels with an original electronic document is provided. An author of an electronic document may generate a transient electronic dictionary that is linked with the original electronic document such that the transient electronic dictionary is transmitted along with the original electronic document when the original electronic document is distributed. At a recipient computer system, when the original electronic document is accessed, the associated transient electronic dictionary is loaded by the word processing application. The loaded transient electronic dictionary is used to expand the permanent electronic dictionary present in the recipient computer system temporarily. The word processing application may then resolve words in the original electronic document using the loaded transient electronic dictionary entries.

Abstract: Mechanisms for change management of interfaces in a distributed computer system are provided in which there are multiple versions of an interface describing communication between distributed client and server applications. The mechanisms include providing an indication with a response to an operation of an interface that an alternative interface is available. The information can include: a time interval in which a client application must contact a server application using the version of the interface, a reference to a succeeding version of the interface; and/or an indication of an expiry date and time of an interface. The interface itself is used to communicate version and validity information and change to client applications.

Abstract: A radio frequency identifier (RFID) active/passive tag is provided to identify failed sub-CRU and location within a higher level CRU. When an error occurs on the base blade or within one of the sub-CRUs, the embedded processor writes failure information to the RFID. RFID tags may also contain data identifying the locations, of the sub-CRUs of the blade. Thus, when there is a failure, the RFID may report the failed component as well as the location of a failed sub-CRU. Sub-CRUs may also include an embedded processor and RFID tag. When a service action is initiated to repair or replace a blade, the RFID tag may be read by a RFID reader. The RFID reader device may then present failure information, including the identification of the failed sub-CRU and other associated information to the operator. The RFID reader device may also request associated information from a server computer.

Abstract: A clock control hierarchy is provided that is comprised of synchronous and asynchronous hold request signals that are used to start and stop functional units of a chip. Pervasive logic is provided that uses a synchronous “chip hold” signal and asynchronous latch/functional unit hold signals to individually target functional units and latches that are to remain in a held state once the “chip hold” state is released. With the present invention, a chip hold request is first activated followed by scannable latch and non-scannable latch hold requests being activated to identify which latches will be clocked or not clocked when the chip hold is released. Functional unit hold signals are activated to place certain ones of the functional units of the chip in a hold state. The chip hold request is deactivated and the chip operates with the selected functional units and latches being maintained in a held state.

Abstract: Mechanisms to identify and speculatively execute future instructions during a stall condition are provided. In speculative mode, instruction operands may be invalid due to a number of reasons. Dependency and dirty bits are tracked and used to determine which speculative instructions are valid for execution. A modified value register storage and bit vector are used to improve the availability of speculative results that would otherwise be discarded once they leave the execution pipeline because they cannot be written to the architected registers. The modified general purpose registers are used to store speculative results when the corresponding instruction reaches writeback and the modified bit vector tracks the results that have been stored there. Younger speculative instructions that do not bypass directly from older instructions use this modified data when the corresponding bit in the modified bit vector indicates the data has been modified. Otherwise, data from the architected registers is used.