Patents Represented by Attorney Steven A. Shaw
  • Patent number: 5713000
    Abstract: Within a data processing system, data transfer between a host device and a slave device is accomplished with only one write operation. The write operation performed by the host device, such as a central processing unit, is performed to an alias destination address, which is related to the destination address by an offset number. The data included within the write operation includes the source address of the data to be transferred. Such a data transfer operation could be utilized to transfer data to a display adapter for display of video related data on a display device.
    Type: Grant
    Filed: June 1, 1995
    Date of Patent: January 27, 1998
    Assignee: Cirrus Logic, Inc.
    Inventor: Michael Kerry Larson
  • Patent number: 5712688
    Abstract: In a graphics card of a computer, a circuit is provided for displaying graphic presentations generated by the card on an external TV set. A TV adapter controls a horizontal state machine of a CRT controller so as to delay generation of CRT timing signals by a time period variable with horizontal lines. As a result, a composite video signal is provided with a time-base variable front porch to simulate VTR video signals. In response to the generated composite video signal, the TV set switches into a VTR mode to disable a comb filter used for separating luminance and chrominance components of a broadcast television signal.
    Type: Grant
    Filed: December 3, 1996
    Date of Patent: January 27, 1998
    Assignee: Cirrus Logic, Inc.
    Inventor: Alexander J. Eglit
  • Patent number: 5706478
    Abstract: A processor for executing display list command packets in processor or coprocessor mode of execution. The processor dynamically switches between the two modes based on the commands or interrupts received. Each display list packet includes a plurality of commands associated with a particular function, where each command includes a field for identifying the number of parameters associated with the command, if any. The parameters immediately follow the instruction in the instruction stream in a sequential format, eliminating address dependency. Each command preferably conforms to the same format regardless of location and mode of execution, so that the software and driver is simplified by not having to generate different code for different locations and modes. Thus, a host CPU executing an application program decides whether certain commands and command packets reside in system memory or within a local memory associated with the processor.
    Type: Grant
    Filed: November 14, 1994
    Date of Patent: January 6, 1998
    Assignee: Cirrus Logic, Inc.
    Inventor: Thomas Anthony Dye
  • Patent number: 5701477
    Abstract: An apparatus and method of replacing the Master Boot Record with an installation code which retains compatibility with any disk partitioning or formatting utility that uses the system's BIOS to access the disk is disclosed. The Master Boot Record which is generally located on cylinder 0, head 0, sector 1 on a disk drive is replaced with a new BIOS loader and BIOS extension code. The BIOS loader determines the location in memory to load the new BIOS and updates the interrupt table. Upon completion of initialization, the new BIOS returns control to the BIOS Boot loader which requests the BIOS to load sector 1, head 0, track 0 to memory and then transfers control to it. The newly loaded BIOS extension redirects the request for this particular sector from 0/0/1 to the highest commonly available sector for cylinder 0 and track 0. Thereafter, all utilities which require access to the Master Boot Record will be transparently re-directed.
    Type: Grant
    Filed: March 30, 1995
    Date of Patent: December 23, 1997
    Assignee: Cirrus Logic, Inc.
    Inventor: Edward John Chejlava, Jr.
  • Patent number: 5699498
    Abstract: A computer system includes a host processor, a system memory, a display unit, a pointer device, a VGA controller, and a display memory. The VGA controller communicates with the display memory through an 8-byte wide data bus such that each byte is controlled by a separate column address strobe.
    Type: Grant
    Filed: May 23, 1995
    Date of Patent: December 16, 1997
    Assignee: Cirrus Logic, Inc.
    Inventor: Ali Noorbakhsh
  • Patent number: 5657055
    Abstract: A graphics controller that uses two MREQ priority levels (low and high) to retrieve display data from a frame buffer into a CRT FIFO. The graphics controller sends the high priority MREQ signal to a host controller if the data level in the CRT FIFO is below a low level water mark. The graphics controller sends the low priority MREQ signal if the data level in the CRT FIFO is between a high level water mark and a low level water mark, and if a system memory bus is idle. The host controller grants access of the system memory bus to the graphics controller with a higher priority (i.e. above that of other devices such as CPU and I/O devices) in response to the high priority MREQ signal, and with a lower priority in response to the low priority MREQ signal. Upon being granted access to the system memory bus, the graphics controller retrieves display data from the frame buffer.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: August 12, 1997
    Assignee: Cirrus Logic, Inc.
    Inventors: Arvind K. Kansal, Thomas C. Yip
  • Patent number: 5619703
    Abstract: A peripheral device capable of generating interrupt request signals compliant with the Industry Standard Architecture (ISA) protocol, and the Peripheral Component Interconnect (PCI) protocol. The peripheral device comprises a signal generator block which selectively generates either the interrupt request signals of the PCI protocol or a set of bits representative of interrupt request signals of the ISA protocol. The set of bits are transferred serially to a converter circuit which generates the interrupt request signals of the ISA protocol based on the bits. The signal generator block generates bits in such a way as to support both pulse mode and level mode interrupt request signals for the ISA protocol.
    Type: Grant
    Filed: June 6, 1995
    Date of Patent: April 8, 1997
    Assignee: Cirrus Logic, Inc.
    Inventors: Reza G. Omid, Sanjiv D. Pathak, Jafar Naji, Stephen A. Smith, Sriram Ramamurthy, Jihad Y. Abudayyeh, Kasturiraman Gopalaswamy
  • Patent number: 5606660
    Abstract: A microprocessor-controlled solid state storage system having a controller and non-volatile memory for storing firmware code therein. The controller includes first memory for storing firmware code transferred from the non-volatile memory, and second memory including primitive firmware code stored therein causing execution of a microprocessor for transferring the firmware code from reserved blocks in the non-volatile memory into the first memory upon initialization of the storage system and causing calculation of a checksum for verification of the integrity of the firmware code.
    Type: Grant
    Filed: October 21, 1994
    Date of Patent: February 25, 1997
    Assignee: Lexar Microsystems, Inc.
    Inventors: Petro Estakhri, Robert Reid, Berhanu Iman
  • Patent number: 5446765
    Abstract: The invention doubles the bit rate for a given media bandwidth as compared to, for example, Manchester encoding. It is applicable to serial transmission or storage of digital data. An arbitrary NRZ data stream is first encoded by a pre-encoding method, such as Manchester, that combines clock and data to represent a single NRZ bit in one clock cycle. A toggle flip flop then re-encodes the pre-encoded waveform, thus generating a double toggle (DT) encoded waveform, which spreads the spectral energy over a larger bandwidth and encodes two NRZ data bits within one transmission clock cycle. In the case of Manchester pre-encoding, data is decoded by determining if there are transitions nearly synchronous with an edge of the recovered clock. For other pre-encoding methods, decoded data is determined by the length of the transition period and the edge polarity of the recovered clock at the leading edge of the transition within the DT encoded waveform.
    Type: Grant
    Filed: August 17, 1994
    Date of Patent: August 29, 1995
    Assignee: Cirrus Logic, Inc.
    Inventor: Geary L. Leger