Abstract: A graphics system includes a graphics processor for rendering graphics primitives with a list of display parameters. A host processor generates a display list which includes a XY address for rendering the graphics primitives. A graphics processor which includes internal fetch and store static random access memory (SRAM)devices for storing pixel fetched from an external memory device and processed in the graphics processor respectively. The graphics processor also includes a pixel data striping control logic which determines whether fetch and store requests by the graphics processor crosses an X boundary in the internal SRAM devices. If a fetch or store request crosses an X boundary, the memory control logic stripes the access into separate blocks of pixel data for each access which are then simultaneously accessed during a single data request cycle.

Abstract: A processing system 100 is disclosed which includes a system master 101, a system bus 102 coupled to the master, and a plurality of bus interface circuits 106 coupled to bus 102. A first one of the bus interfaces 106 includes a mapping signal input coupled to the master and a mapping signal output, the first bus interface 106 operable to latch-in at least one first selected address bit presented by the master on the system bus in response to a mapping enable signal received at the mapping signal input from the master 101. A second bus interface 106 is provided coupled to the bus 102 and having a mapping signal input coupled to the mapping signal output of first bus interface 106, the second bus interface 106 operable to latch-in at least one second selected address bit presented by the master 101 on the bus 102 in response to a second mapping enable signal received at the mapping input of the second bus interface 106 from the first bus interface 106.

Abstract: A graphics controller circuit in a computer system for generating display signals to a television. The graphics controller circuit may downscale a display image to generate a downscaled image. While downscaling, the graphics controller circuit may generate each horizontal line of a downscaled image from a different number of horizontal lines of a display image. In addition, the graphics controller circuit uses clock signals with different frequencies so as to generate each horizontal line of the downscaled image in the same amount of time. The clock frequencies are designed to generate downscaled image horizontal lines at an input rate required for a television. In effect, the graphics controller circuit may avoid dropping display image horizontal lines while downscaling, and also reduce flicker while displaying the downscaled image on a television.

Abstract: A graphics system includes a graphics processor for rendering graphics primitives with a list of display parameters. A host processor generates a display list which includes a XY address for rendering the graphics primitives. A graphics processor which includes an arbitration logic device enables the graphics processor to temporarily arbitrate shared resources to dissimilar graphics drawing engines. The arbitration logic allows data from the dissimilar drawing engines to be prioritized, depending on the configuration of the underlying computer system, for accessing shared resources.

Abstract: A graphics system includes a graphics processor for rendering graphics primitives with a list of display parameters. A host processor generates a display list which includes a XY address for rendering the graphics primitives. A graphics processor which includes a command address feed logic device decodes the display list to determine the register locations in a register file to fill with data. The command address feed logic device decodes the display list and orders a group of registers in the register file in order to perform a sequential write to the register file. By sequentially ordering the register file locations, the command address feed logic device is able to write null or zero data values to the register locations which are not needed to render a primitive, while maintaining a single write cycle to the register file.

Abstract: A graphics system includes a graphics processor for rendering graphics primitives with a list of display parameters. A host processor generates a display list which includes a XY address for rendering the graphics primitives. A graphics processor which includes internal fetch and store static random access memory (SRAM)devices for storing pixel fetched from an external memory device and processed in the graphics processor respectively. The graphics processor also includes a memory control logic which determines whether fetch and store requests by the graphics processor crosses an X boundary in the internal SRAM devices. If a fetch or store request crosses an X boundary, the memory control logic divides the access into two separate accesses which are then non-sequentially accessed during a single data request cycle. By non-sequentially fetching and storing data, the graphics processor is able to execute a single X crossing for multiple Y scan-line operations to fetch or store data internally.

Abstract: A built-in self test (BIST) for an integrated circuit (IC) including a large logic section, a large dynamic random access memory (DRAM), and a smaller static RAM (SRAM). Additional logic circuitry is included within the IC to enable the IC to test the DRAM, that is, a built-in self test of the DRAM. The DRAM test program is stored in the SRAM by the VLSI tester, and portions of the existing logic circuitry may be used for the memory testing. The VLSI tester initiates the DRAM test and inspects the results of the test but does immediately participate in the DRAM testing. Thereby, a VLSI tester can test both the logic and DRAM portions of the IC, eliminating the need for separate memory test equipment.

Abstract: A graphics system includes a graphics controller for rendering polygons with texture using an improved MIP mapping technique. The graphics controller includes a polygon engine for rendering the pixels in a polygon and a texture map engine for selecting texture elements ("texels") from an appropriate texture map to be applied to the pixels rendered by the polygon engine. The texture map engine generates texel coordinate values from pixel coordinate values provided by the polygon engine. The appropriate texture map is selected from a set of texture maps each varying from the others by the level of detail of the texture in each map. The graphics controller selects the appropriate level of detail texture map to use to increase speed, efficiency, and realism quality of the graphics system. The determination as to which level of detail texture map is appropriate is made by computing the area bounded by adjacent texel coordinates generated by the texture map engine.

Abstract: In a computer system, a peripheral graphics device (PGD) accesses a graphics buffer (GB) wherein the GB physical pages can be contiguous or discontiguous. A request is received to allocate memory for a GB of a predetermined size and handle. The number of pages within the size parameter is determined based on the page size used by the computer system and the buffer size needed. A first memory block is allocated for storing the GB and locked to prevent swapping. A starting virtual address of a CPU page table (CPU/PT) is accessed and mapped to a starting logical address to allow traversal of the CPU/PT by a user application. A second memory block is allocated for building a graphics device page table (GDPT) that can be accessed by a PGD. The logical address of each GB page is sequentially accessed and the corresponding physical address of each GB page is determined from the CPU/PT. The logical and physical addresses of each GB page are stored into the GDPT.

Abstract: A memory 201 comprising an array 302 of memory cells, an address decoder 303, 305 for accessing a selected one of the cells in response to at least one address bit, and a programmable array 311 for selectively presenting the at least one address bit to the address decoder 303, 305 in response to a control signal.

Abstract: A graphics system including a frame buffer having two or more buffers, a graphics processor and system memory. The graphics processor includes rendering logic, display logic and a buffer switch memory that stores an address. The display logic reads the address from the buffer switch memory and retrieves rendered data for display from one of the buffers. The rendering logic retrieves a next display list from the system memory after a continue indication is provided, renders the retrieved display list into another buffer, writes an address corresponding to the other buffer into the buffer switch memory and clears the continue indication. The continue indication may be a separate bit or a continue flag provided within each display list. The rendering logic sequences through the plurality of buffers in this manner to render a plurality of display lists. If only two buffers are provided, then the buffer switch memory includes an arm bit and the rendering logic sets the arm bit after rendering each display list.

Abstract: A graphics system includes a graphics processor for rendering graphics primitives with a list of display parameters. A host processor generates a display list which includes an XY address for rendering the graphics primitives. A graphics processor, which includes a bypass logic circuit, enables the graphics processor to temporarily store display list commands in an internal storage device while previously fetched display list data is being processed. The bypass logic circuit allows the graphics processor to bypass the internal storage device and write fetched command directly to an execution unit in the graphics processor. By having the bypass capabilities, the graphics processor is able to optimize the internal storing of commands in the display list in the internal storage unit.

Abstract: A graphics controller circuit comprising a plurality of pipelines for performing a set of operations on a stream of input pixel data to generate at least a first operand and a second operand. A rasterop unit in the graphics controller circuit may receive the first operand and the second operand, and execute a raster operation using the first operand and the second operand to generate a set of display pixel data. The graphics controller circuit may further comprise a transparency unit for generating a write enable mask corresponding to the set of display pixel data. A display memory may selectively store or block the set of display pixel data according to the write enable mask. As the graphics controller generates display signals from the display data stored in display memory, a transparency operation may be performed.

Abstract: A memory 200 comprising a first memory bank 201a including an array 202a of memory cells and a circuitry 203a, 205a for addressing a location within array 202a. Memory 200 further includes a second memory bank 201b including an array 202b of memory cells and circuitry 203b, 205b for addressing location within array 202b. Circuitry 203, 206, 207 is included for selectively pipelining a plurality of serially received words of address bits to the banks 201 during precharge of the banks.

Abstract: A synchronized frequency hopping method and apparatus for use in a cellular communication system where the cellular communication systems has a plurality of cells and a plurality of frequencies available to be assigned to the cells. At predetermined times, cells in the system synchronously change or hop to a new frequency. The new frequency to which a cell hops to may be a function of the present frequency the cell is assigned. In addition, synchronized frequency hopping may occur at predetermined intervals and the pattern of hopping may periodically repeat. This technique limits the period of time a non-system source of interference may impair communications in any cell since the cell hops to different frequencies periodically.

Abstract: A CD-R controller for recording on a CD-R disk a signal representative of a set of signal data. The CD-R controller includes a buffer manager for receiving a command such as a CUE-sheet, and sends the command to a micro-controller. The micro-controller generates instructions corresponding to each command by using information stored in a ROM. The buffer manager stores the instructions in a buffer and then sends the instructions to a CD-R formatter. Buffer manager may then send signal data corresponding to the instructions to a recording circuit. CD-R formatter generates control signals to the recording circuit from the instructions. The control signals cause recording circuit to generate recording signals to a CD-R drive. The CD-R drive may record the signal representative of the signal data in response to the recording signals.

Abstract: A process and implementing computer system for graphics applications in which polygon information is organized, stored and transferred in terms of "UV" addressable designated texel blocks of information within the graphics system. The texel information blocks are re-configured and remapped from normal graphics "UV" configuration to "XY" addressable configuration in order to allow storage of the texel blocks in otherwise unused sections of the relatively fast frame buffer memory.

Abstract: A method and apparatus for determining representative values for the chrominance components to be associated with a plurality of luminance components in a horizontally shrunken or stretched image for graphics controllers wherein display image data is stored in a buffer memory in a form associating a single set of U and V chrominance components with a plurality of Y luminance values. For a four to one shrinkage of an image in a format associating one set of chrominance components with four pixel luminance values wherein each pixel luminance value in the shrunken image initially has as associated set of chrominance components U.sub.0, U.sub.1, U.sub.2 and U.sub.3 and V.sub.0, V.sub.1, V.sub.2 and V.sub.3, the multiple values of the chrominance components are sequentially accumulated in a 3/4:1/4 ratio in such a manner as to provide an approximate average value for U and V for each set of four pixel luminance values in the shrunken image.

Abstract: A memory includes a bitline comprised of 2 half-bitlines with at least one cell coupled to each of the half-bitlines. A sense amplifier for detecting a voltage difference is coupled between the half-bitlines. A control signal controls the current through the sense amplifier. A method is provided for sensing data by precharging a pair of half-bitlines, activating a storage cell coupled to one half-bitline and reference cell coupled to its complement. A sense amplifier senses the voltage difference between the half-bitlines by initiating current flow through the sense amplifier during an intitial period and increasing the current flow during a subsequent period.

Abstract: A method of adapting a hand test socket for use in a workpress assembly includes: providing a hand test socket having a base and a top cover. The top cover includes a clamp. The method includes the step: removing the top cover and the clamp and configuring the clamp for use in a workpress assembly. The step of configuring the clamp includes forming a frame and attaching the clamp to the frame.