Abstract: An SDRAM memory controller that provides both burst four and single data transfers while keeping the SDRAM in burst four mode. A memory controller uses a DQMB?7:0! signal and a precharge command to stop the transference of data on the data bus during the time that the last 3 data elements would have been transferred. Specifically, during a single read, DQMB?7:0! is set high for two clock cycles causing the data bus to float during the time that the second and third data elements would have been on the bus. During a single write, DQMB?7:0! is set high for two clock cycles thereby preventing the second and third data elements from being written to memory. During a read, the precharge command causes the bus to float during the time the fourth element would have been on the bus. During a write, the precharge command prevents the fourth data element from being written.

Abstract: A process and implementing computer system for graphics applications in which polygons from a frame buffer, which may have three dimensional depth, color and other characteristics, are compactly reassembled and drawn to a fast memory for high speed and highly efficient processing. Polygons are divided into shaped segments which correspond to the shapes of the polygons. Corresponding memory storage references to the polygon objects themselves enable optimal processing efficiency and speed.

Abstract: An improved user interface for a cellular telephone system subscriber unit, including the following functions: (1) a predictive keyboard input method for speeding up input on a telephone with a space limited keyboard; (2) a word completion method for speeding up input; (3) a distinctive signaling method useful in a dual-mode or tri-mode cellular phone system that incorporates both voice call functionality and data messaging functionality; (4) a secret message method that permits secret messages to be received by an authorized user of a cellular telephone that includes a data messaging capability; (5) a message screening method that permits a user to set a message screening mode in a cellular telephone; (6) an improved "scratchpad" method which permits a user to enter a telephone number into a storage register of a cellular telephone while in the middle of a voice call, visually verify the entry, and then save the number to a rapid redial location for later use; (7) a global search method for searching text st

Abstract: An automatic step generator that monitors and corrects the sampling rate in a video signal. The invention isolates a sampling window in the prevailing sampling rate, the window advantageously being 144 lines for NTSC, or 231 lines for PAL, or some other preselected window wherein the sample count therein at an ideal sampling rate approximates an integer power of 2. The invention then calculates the numeric difference between that ideal sample count in the window and the preselected integer power of 2. The actual sample count in the window is then determined, and is adjusted by the numeric difference between the ideal count and the integer power of 2. Variations in this adjusted actual sample count and the integer power of 2 will thus represent variations between the actual sampling rate and the ideal sampling rate. A step value to correct the actual sampling rate to achieve the ideal rate may then be derived by dividing the adjusted actual sample count by the integer power of 2.

Abstract: A display controller to upscale a source video image for display on a display unit of a computer system. An encoder circuit in the display controller circuit stores in a local memory pixel data of previous scan lines required for interpolation in a compressed format using differential pulse code modulation (DPCM) scheme. Encoder circuit avoids a slope overload condition by generating compressed data for a first pixel of each scan line by using the first pixel itself as a reference. Encoder circuit generates compressed data for other pixels by using at least one prior pixel in the corresponding scan line. A decoder circuit decompresses the pixel data into original format prior to sending to an interpolator. The interpolator receives a present scan line and the decompressed data of previous scan lines, and interpolates the received pixels to generate additional pixels required for upscaling the source video image.

Abstract: A system 500 is provided for transferring signals across a bus which includes a power source 550 operating between a high voltage rail at a first supply voltage level and a low voltage rail at a second supply voltage rail, power source 550 generating a third supply voltage level on an output thereto. The third supply voltage level is greater than the first supply voltage level. A processing circuitry 103, 104 is included for generating a plurality of data signals each having a first voltage swing between a first logic high level substantially equal to the first supply voltage level and a first logic low level substantially equal to the second supply voltage level. The system additionally includes a plurality of buffers, 520, each buffer 520 being coupled to the power source 550 output and receiving a selected one of the data signals.

Abstract: A memory subsystem with multiple memory banks each having an array of memory cells includes address control circuitry for presenting address bits to the row and column decoders of the memory banks and switching the row and column addresses presented to the different banks. Address control circuitry may be a translation look ahead buffer or may include an address translator, a row address buffer, and a column address buffer. The memory subsystem may also include input/output circuitry for inputting address bits in response to row address strobe and column address strobe signals. Input/output circuitry may allow both serial and parallel access to the multiple memory banks.

Abstract: A process and implementing computer system for graphics applications in which polygons from a frame buffer, which may have three dimensional depth, color and other characteristics, are compactly reassembled and drawn to a fast memory for high speed and highly efficient processing. Polygons are divided into shaped segments which correspond to the shapes of the polygons. Corresponding memory storage references to the polygon objects themselves enable optimal processing efficiency and speed.

Abstract: A method and apparatus for improving pixel data write operations to a tile-based frame buffer. The present invention includes a byte enable first-in first-out register for storing byte enable data for masking pixel data writes to a tile based frame buffer when the pixel data crosses a tile boundary. Pixel data generated by a graphics processor to the frame buffer may traverse multiple tiles. With each 64-bits of pixel data generated, a corresponding byte of byte enable data is generated as mask data for the frame buffer. The byte enable circuit of the present invention may be implemented as a circular shift register to allow the byte enable data to be shifted, rather than being "popped" after the pixel data has been written to the frame buffer. By shifting data rather than "popping" data, the byte enable circuit is able to retain portions of the byte enable data to enable a correct write of a pixel word which may traverse tile boundaries.

Abstract: A process for producing a wide range of shades in images that are presented in successive frames on image fields on opto-electronic display means having at least one illumination element at each of a plurality of pixel locations. Each pixel location, for example, may have a red, a green and a blue illumination element. The display is divided into uniformly-sized display neighborhoods.

Abstract: A transaction queue for transferring data between a host bus and an internal system bus within a graphics controller is disclosed. The queue comprises a First In First Out (FIFO) memory having independent clocks for reading and writing. The queue accommodates address information, data, command information, byte enable information, decode information, and a tag. The tag is a 2 bit field used to identify the queued entries as address, last data, and burst data. In a preferred embodiment, single transactions are written to the queue with no wait states. In the case of an address entry, the address associated with the transaction is stored in the queue along with the command and decode information. A tag is also included that identifies the entry as an address. In the case of a final data entry, the data is stored in the next entry along with the byte enable information and a tag to indicate it is the last data of the transaction.

Abstract: A precise current cell for a digital-to-analog (D/A) convertor circuit is designed to compensate for manufacturing process variations. The cell uses a cascoded transistor chain to control the output voltage and isolate voltage supply noise. An external (off-chip) bias current is fed into a cascoded biasing string of eight transistors, which are further mirrored to the current cell itself. The biasing scheme accounts for manufacturing process variations in the chip, which leads to very precise current being replicated at the output of the D/A circuit. Current steering and an improved shunt path within the current cell minimizes voltage swings during switching of the current cell. This allows for faster switching of the cell while minimizing noise coupling due to the voltage swings. The current cell also has an associated biasing stage. This biasing stage allows for improved matching within the current cell, resulting in improved accuracy of conversion.

Abstract: A host adapter of a computer system includes combinational logic circuit eliminating both positive and negative-glitches from an input signal. The circuit comprises two NAND gates and two delay elements in one embodiment. The delay introduced by second delay element is twice that of the first delay element. The first delay element receives as input the input signal. The first NAND gate receives as inputs the input signal and the output of the first delay element. The second delay element receives as input the output of the first NAND gate. The second NAND gate receives as inputs the output of the first NAND gate and the output of the second delay element. The output of the second NAND gate comprises the input signal with both positive and negative glitches having a duration of less than the delay of the first delay element eliminated. In a second embodiment, the two NAND gates are replaced by two NOR gates.

Abstract: A VGA compatible graphics controller receives character data, attribute data and font data, each of which are stored in different planes of a display memory. The font data comprises bit maps of at least two character fonts, which may be user fonts or default fonts loaded from a controller BIOS. The video controller detects attempts by a host CPU to write data into plane two of display memory (where character font bit maps reside). The address generated by the host CPU is scrambled to produce a video font cache address. The character font bit maps are stored in a video font cache at the scrambled address. The font select bits of the CPU generated address are used as a byte select to store a particular font at a byte location at a selected video font cache address. In the preferred embodiment, eight fonts may be stored in the video font cache, one scan line each font of each character as a different byte at each address of the video font cache in a 64 bit wide DRAM.

Abstract: An arbitration controller that temporarily raises the priority of a graphic device's HWM request above that of the BitBLT engine while that device's LWM request is being served. In this manner, the BitBLT engine cannot interrupt the transfer of data to the graphics device. Each device capable of issuing memory access requests is categorized into one of four classes. The LWM requests are the highest priority requests, followed by CPU memory access requests, then BitBLT engine requests, and finally by HWM requests. When a LWM request is granted, the requesting device's HWM request is elevated to a priority between the CPU and the BitBLT engine. Once the LWM request is complete, the HWM request is served until either it completes, the CPU issues a memory access request, or another LWM request occurs.

Abstract: An arrangement and method for adjusting the brightness of an image signal having digital pixel values to produce brightness adjusted output pixel values is provided with an adder and lower and upper clamp circuits. The adder adds a brightness value to the digital pixel values of the image signal to produce adjusted pixel values and a carry-out signal. The lower clamp circuit clamps the adjusted pixel values to a lowest output pixel value when the carry-out signal and the brightness value indicate that addition of the brightness value to the digital pixel values produces adjusted pixel values below the lowest output pixel value. The upper clamp circuit clamps the adjusted pixel values to a highest output pixel value when the carry-out signal and the brightness value indicate that addition of the brightness value to the digital pixel values produces adjusted pixel values above the highest output pixel value.

Abstract: An apparatus and method for efficiently receiving a long string of short data packets. Storing a long string of short data packets received from external devices can be inefficient in terms of system resources such as system memory and CPU time. In the preferred embodiment of the present invention, both the number of data packets in the FIFO buffer and the demand of system memory are monitored. A FIFO buffer of at least 32 bytes deep and having a packet-based threshold is implemented to monitor the number of data packets in the FIFO buffer. When the number of data packets in the FIFO buffer is equal to or exceeds the threshold and there is a predetermined number of free buffer memory available, data is transferred from the FIFO buffer to system memory. The number of data packets transferred from the FIFO buffer is also monitored to control the amount of data transfer. Any data stuck inside the FIFO buffer for a predetermined period of time is automatically unloaded.

Abstract: A memory system 104 is provided which includes an array 200 of memory cells arranged in rows and columns. Circuitry 207, 208, 209, 210 is also provided for selectively performing logic operations on a bit of data stored in a selected memory cell using a bit of received modifying data. Circuitry 207, 208, 209, 210 for performing logic operations is operable during an AND operation to write the bit of modifying data into the selected memory cell when the bit of modifying data is a logic zero and maintains an existing bit stored in the selected cell when the bit of modifying data is a logic one.

Abstract: A method and apparatus to stretch video images in a graphics controller chip of a computer system. The graphics controller chip fetches four pixel data comprising two pixel data each from a first scan line and a second scan line of a source video image, and generates a set of additional pixels in a rectangular area defined by the four pixels. The graphics controller chip stores the pixels of rectangular portions in a display memory, and displays the pixel data of the stretched video image in a scan line order.

Abstract: An adaptive dithering apparatus analyzes an input video signal as a function of available primary shades and produces a select signal whose value is a function of the desired shade represented by the input video signal and of the available primary shades. A combiner combines the input video signal with a selected one of a plurality of dither signals to generate a dithered input video signal. The one dither signal is selected under the control of the select signal. Finally, an adjustor receives the dithered input video signal, the available shade signal, and the select signal and, under the control of the select signal, adjusts the dithered input video signal to have a value equal to one of the available primary shades. Thus, an input video signal may be dithered with a dither signal that is optimized for dithering an input signal that falls into a particular range of desired shades. That is, a different dither signal may be employed for each possible spacing of adjacent available primary shades.