Abstract: A system is provided for transferring information across a conductor 203. Transmitting circuitry 210 receives information in the form of a first signal having a first voltage swing and, in response, outputs a second signal having a second voltage swing. The first voltage swing is between a first high voltage and a first low voltage and the second voltage swing is between a second high voltage less than the first high voltage and a second low voltage greater than the first low voltage. The second high voltage is substantially equal to a voltage level of a first voltage rail to which the transmitting circuitry 210 is coupled and the second low voltage is substantially equal to a voltage level of a second voltage rail to which the transmitting circuitry 210 is coupled. The conductor 203 carries the second signal output from the transmitting circuitry 210.

Abstract: A memory 20 includes a first array 100 and a second array 102 of memory cells. A first data port 118 allows for the exchange of data with the first array 100 and a second data port 120 allows for the exchange of data with the second array 102. Memory system 20 also includes a circuitry 122 for controlling data exchanges in a selected mode with the first array 100 via the first data port 118 and with the second array 102 via the second data port 120, the exchanges with the first and second arrays 100 and 102 being asynchronous.

Abstract: A process and implementing computer system for graphics applications in which polygon information, including transparency, color and other polygon characteristics, is organized, stored and transferred in terms of areas or tiled blocks of information in a matrix configuration. The polygon bytes of texel information are organized in an exemplary 8.times.8 matrix row and column format in the graphics subsystem for improved cache-hit efficiency and translated to and from the linear addressing scheme of a host storage device when the host storage is accessed to refill the graphics cache. The bytes comprising the memory tiles of polygon information are arranged such that a complete tile of information is transferred in one burst-mode host memory access to minimize normal multi-line access arbitration and other typical access delays.

Abstract: A video controller for controlling at least two video displays having independent refresh rates and pixel resolutions. In a first embodiment, two separate data paths are provided within a video controller for each video display (e.g., CRT and LCD). Taking advantage of the increased bandwidth of 64 bit wide DRAMS, data for each data path may be retrieved in separate read cycles. Each datapath may operate at its own clock frequency characteristic of refresh rate and pixel resolution. The dual data path embodiment also reduces the complexity of the software model needed to drive such dual displays. IN an alternative embodiment, a single data path may be provided within a video controller to drive data for two video displays having independent refresh rates and pixel resolutions. A data "tag" (extra bit) is attached to each word or dword passing through the data path indicating the destination (e.g., CRT or LCD) of the video data. At the output of the data path, separate FIFOs (e.g.

Abstract: A multimedia system includes an audio/video decompresser/decoder for decompressing/decoding a compressed/encoded audio/video data stream in order to generate video images for display on a display device and to generate audio signals for audible reproduction. The multimedia system includes an integrated system and video decoder that has a novel memory controller and a novel method for displaying complete decoded/decompressed video frames on a display device without tearing. By use of selective storage of decoded/decompressed video frames in memory, tearing is prevented but information for predicting motion of a video segment is preserved.

Abstract: An apparatus for capturing and decoding the teletext data from a television signal and displaying the teletext data, along with the video picture, in a windowing environment on the monitor of a personal computer system. The teletext data decoder retrieves the lines of teletext data stored in the frame buffer with the rest of the video frames, decodes the teletext data in software and stores the teletext characters directly in system memory for further processing and display in user-defined windows on the PC monitor.

Abstract: A method and apparatus for analyzing each microinstruction in a microinstruction-based electronic circuit having a plurality of registers to determine which registers in a processing cycle are not involved in the processing cycle, and preventing those registers from being clocked during such processing cycle. Hence, inactive registers during a processing cycle do not consume power at the level of active registers, thus lowering overall power usage by any system employing such gated-clock registers.

Abstract: A memory 600 including an array of memory cells 201 and a plurality of input/output terminals 220 for receiving control bits during control cycles and accessing selected ones of the cells 201 during data access cycles. A command bit input terminal 221 is provided for receiving command bits for initiating the control cycles and a mapping input terminal 222 is provided for receiving a mapping enable signal to initiate a mapping mode. Circuitry 215/ 216 is provided for decoding control bits received during at least one control cycle occurring during a mapping mode for allowing a mapping of a set of addresses for accessing the cells of the array 201.

Abstract: A decoder is disclosed for decoding MPEG video bitstreams encoded in any color space encoding format and outputting the decoded video bitstream to different sized windows. Both MPEG decompression and color space decoding and conversion are performed on the bitstreams within the same decoder. The disclosed decoder may be programmed to output the decoded video bitstream in any of three primary color space formats comprising YUV 4:2:0, YUV 4:2:2, and YUV 4:4:4. The decoder may also output the decoded bitstream to different sized windows using Discrete Cosine Transform (DCT) based image resizing.

Abstract: A memory including a plurality of input/output terminals 220 for exchanging data bits during a data access cycle and receiving command and control bits during a command and control cycle. The memory further includes an array of memory cells 201, a data input/output circuitry for transferring data between the input/output terminals and the array of memory cells during the data access cycle, and control circuitry for controlling operations of the memory in response to command and control bits received at the input/output terminals during the command and control cycle.

Abstract: A file access history attribute may be encoded and stored with a file in a computer memory. The file access history attribute may provide information as to the date of most recent access and the level of access on which date. In addition, the file access history attribute may provide information concerning recent file history (e.g., previous nine days), quarterly history (e.g., 80 days preceding the previous nine days), as well as long-term history (e.g., beyond the 80 day period). The encoding technique of the present invention may compress file access history information into a compact file access history attribute (e.g., six to twelve bytes). Disk caching software, for maintaining files in a hard drive of a local computer coupled to a network, may utilize the file access history attribute in deciding which files are to be stored in the local hard drive and which should be migrated to network storage or archive.

Abstract: A graphics subsystem includes hardware for permitting tile texture data to be dynamically cached internally within the hardware. In addition, the system generates a SHIFT signal to permit automatic adjustment of tile texture parameters to facilitate retrieval of the cached texture maps. The system includes a 1 kbyte static random access memory internally disposed within a graphics processor to facilitate UV caching of the texture maps by the graphics processor. A cache controller also disposed within the graphics processor facilitates tile requests by other resources in the graphics subsystem to the internal static random access memory. The cache controller performs UV tile read hit comparisons and subsequent UV to linear address conversions to read texels from the internal static random access memory.

Abstract: An apparatus for controlling a flat panel display with reduced flicker, particularly during grey scale shading. Three shading pattern lookup tables are provided, one for each sub-pixel color (Red, Blue, Green). Each shading pattern lookup table outputs a plurality of shading pattern duty cycle signals, each representing a different shade level. The phase of the three duty cycle signal patterns may be altered by adding a predetermined offset amount to one or more of the shading pattern lookup table addresses. By altering the phases of the outputs of the shading lookup tables, peak current demand within the flat panel display may be reduced and flicker or strobing of individual pixels may be reduced or eliminated.

Abstract: A memory comprising a first memory bank 201 and a second memory bank 201 includes a plurality of data input/output terminals, a first subset of the plurality of data input/output terminals for accessing the first memory bank and a second subset of the plurality of data input/output terminals for accessing the second memory bank.

Abstract: A multimedia system including an audio/video decoder/decompresser for decoding/decompressing a compressed encoded audio/video data stream to generate video images for display and audio signals for audible reproduction. The multimedia system includes an integrated system and video decoder with an audio/video synchronization circuit for substantially synchronizing the display of video images with audio playback. In addition, a step control is provided to allow for viewing of video images on a frame-by frame basis or to freeze or play video in slow motion. When step control is activated, audio output is muted. Audio data corresponding to displayed video is transmitted to the muted audio decoder. An internal system clock may be suppressed to the system clock counter. An external CPU may provide system clock start times corresponding to video frames to be displayed. The external CPU may increment the system clock counter by a an amount corresponding to the difference between a successive frame or number of frames.

Abstract: A display controller for a computer or the like stored display data in a tiled format in a display memory. Tile shape may be dynamically altered depending upon display mode (resolution, pixel depth, or the like) or other display factors. Tile shape (height versus width) may be optimized for different types of display (e.g., video, text, graphics, or the like). A display memory address conversion apparatus may receive pixel position data (e.g., from a BIT BLT engine or the like) and tile shape data and convert pixel position data to a tiled display memory address.

Abstract: A computer graphics display system and method are described for rendering objects formed of at least one geometric primitive as pixel images which collide or intersect in three dimensional space. A depth buffer stores depth information representing graphics images rendered by the graphics system. Data stored in the depth buffer representing graphics objects displayed in the three dimensional space are partitioned into three portions comprising an identification portion to store information identifying each object rendered in the three dimensional space, an object resolution portion to store data for controlling the resolution of the graphics object on a display screen, and a depth coordinate portion for storing the coordination information of the object rendered in the three dimensional space. A collision detection is provided to detect and determine when two objects collide on the display screen.

Abstract: A method is disclosed for controlling tearing in a display control system which includes first and second buffers, with input of data to a selected one of the buffers controlled by an input pointer and output of data from a selected one of the buffers controlled by an output pointer. Data is first input into the first buffer and substantially simultaneously data is output from the first buffer. The output pointer is then toggled such that data is input into the first buffer and output from the second buffer. Next, the input pointer is toggled, such that it is input into the second buffer and data is output from the second buffer. The output pointer is again toggled such that data is output from the first buffer and input into the second buffer.

Abstract: The invention doubles the bit rate for a given media bandwidth as compared to, for example, Manchester encoding. It is applicable to serial transmission or storage of digital data. An arbitrary NRZ data stream is first encoded by a pre-encoding method, such as Manchester, that combines clock and data to represent a single NRZ bit in one clock cycle. A toggle flip flop then re-encodes the pre-encoded waveform, thus generating a double toggle (DT) encoded waveform, which spreads the spectral energy over a larger bandwidth and encodes two NRZ data bits within one transmission clock cycle. In the case of Manchester pre-encoding, data is decoded by determining if there are transitions nearly synchronous with an edge of the recovered clock. For other pre-encoding methods, decoded data is determined by the length of the transition period and the edge polarity of the recovered clock at the leading edge of the transition within the DT encoded waveform.

Abstract: A computer system having a unified memory architecture (UMA) with a central SDRAM memory can be accessed by multiple devices. Arbitration logic receives and arbitrates among the memory requests. The memory controller indicates when the arbitration logic may issue a grant. The memory controller has two arbitration points during a memory cycle, an early one and a late one. A central processing unit (CPU), or other device, that misses the early arbitration point can still get memory access during the memory cycle by submitting a memory request before the late arbitration point.