Abstract: A semiconductor package is proposed, in which a substrate is formed with a chip bonding area and a plurality of bond fingers surrounding the chip bonding area, and a plurality of bridging elements are disposed in a stagger manner between the chip bonding area and the bond fingers on the substrate. Multiple wire bonding processes are performed to bond first gold wires between the chip and the bridging elements, and bond second gold wires between the bridging elements and the bond fingers. This therefore significantly shortens a wire bonding distance as compared with only one time of wire bonding for electrically connecting the chip to the substrate. As a result, wire bond operability is improved, and the shortened wire bonding distance reduces wire length so as to enhance resistance of the gold wires to mold flow impact during molding, thereby preventing wire sweeping or wire sagging from occurrence.

Abstract: A semiconductor package having a heat sink attached to a substrate is provided. The semiconductor package includes a substrate for mounting at least one semiconductor chip thereon; wherein the semiconductor chip is electrically connected to the substrate and a plurality of positioning holes formed on the substrate for being engaged with a plurality of positioning portions formed on the heat sink, allowing the heat sink to be securely fixed to the substrate. Thus dislocation of the heat sink on the substrate can be effectively prevented during the molding process.

Abstract: A head mounted virtual environment display with high visual resolution and a full field of view is disclosed. The display uses an optical system in which the video displays and corresponding lenses are positioned tangent to hemispheres with centers located at the centers of rotation of a user's eyes. Centering the optical system on the center of rotation of the eye allows both a full field of view and high fidelity visual resolution, without compromising visual resolution. A multi-panel video wall design for the video displays allows each lens facet to image a miniature flat panel display at optical infinity. The flat panel displays are centered on the optical axes of the lens facets. A parallel graphics architecture uses data from high resolution and accuracy head trackers and built-in eye trackers to generate high detail 3D models at high frame rates with minimal perceptible lag.

Abstract: A method of single frequency channel communication is proposed, for use with a communication system having different communication areas of different area codes, allowing messages or signals to be transmitted between two mobile phones located in the same or different communication areas through transmitting stations without the use of electronic switching systems. A message inputted from a sender mobile phone is denoted with area codes of the sender and receiver, and converted to a signal for being transmitted to a transmitting station where the signal is processed and amplified. For message/signal transmission within a single communication area, such that the sender's and receiver's area codes are identical, the signal received by the transmitting station is directly forwarded to the receiver mobile phone.

Abstract: A chip carrier for accommodating a passive component is proposed, allowing at least a chip to be electrically connected to the chip carrier. At least a pair of spaced-apart solder pads are formed on the chip carrier in no interference with the electrical connection between the chip and the chip carrier. A passive component is bonded at its two ends onto the solder pads by solder paste that electrically connects the passive component to the chip carrier. A recessed portion formed between the pair of the solder pads, is associated with a bottom surface of the passive component to form a passage, allowing a resin material for encapsulating the passive component or the chip to pass through and fill the passage, whereby the filled passage can prevent bridging of the solder paste and short circuit of the passive component from occurrence, thereby making yield of fabricated products desirably improved.

Abstract: A data signal line driving circuit is provided with a unit block which corresponds to each set of data signal lines corresponding to the data signal lines for two pixels adjacently provided in the direction of a scanning signal line. Each unit block is provided with a positive polarity system including a level shifter, a D/A converter and a voltage follower for the positive polarity, and a negative polarity system including a level shifter, a D/A converter and a voltage follower for the negative polarity. Further, the ranges of power voltages of the positive polarity voltage follower and the negative polarity voltage follower are respectively the high voltage side half and the low voltage side half of the range of a power voltage of a positive/negative polarity-compatible voltage follower.

Abstract: A trench capacitor with an expanded area for use in a memory cell and a method for making the same are provided. The trench capacitor includes a vertical trench formed in a semiconductor, a doping region formed around a low portion of the trench, a collar isolation layer formed on an inner sidewall of an upper portion of the trench, a doped silicon liner layer formed on a surface of the collar isolation layer, wherein the doped silicon liner layer is electrically connected to the doping region, a dielectric layer formed on a surface of the doped silicon liner layer and inner sidewall of the lower portion of the trench, and a doped silicon material formed inside the trench.

Abstract: A semiconductor package and a method for fabricating the same are proposed, in which a chip is attached to a die pad formed with an opening in a manner that the chip covers the opening and a surface of the chip is partially exposed to the opening. A covering layer is formed on the exposed surface of the chip, so as to fill a gap formed between the chip and the die pad in proximity to the opening, and allow air in the gap to be dissipated. This makes an encapsulant formed for encapsulating the chip and the die pad with no void formed therein, so that no die crack or popcorn effect occurs in the fabricated product, and thus quality and reliability of the semiconductor package can be assured.

Abstract: An apparatus and method for splicing photographic films is disclosed, where the films are conveyed along a path and supported by a track element. Upon being positioned to receive a splice, the films are clamped between a movable splice pad and the track clement. The clamping action produced by the movable splice pad substantially eliminates the problem of film foldovers caused by curling at the trailing end of a film. A splice head is lowered to apply a splice tape to the films, thereby forming the splice. The films are spliced together in a flattened state, producing a continuous web of film which can be wound onto a roll or core for further processing.

Abstract: A photosensitive semiconductor package with a lid is proposed, in which a chip carrier is formed with an encapsulant thereon, and the encapsulant is formed with a cavity for exposing a semiconductor chip mounted on the chip carrier. A top of the encapsulant is structured with a groove and at least a beveled portion that descends toward the groove and is associated with the groove. When a lid is attached onto the encapsulant by using an adhesive, the groove can temporarily retain excess adhesive with its flow being directed toward the groove by the beveled portion, so that undersirable adhesive loss and adhesive flash can both be prevented from occurrence, allowing the appearance of the semiconductor package to be well maintained.

Abstract: A semiconductor package with an embedded heat-dissipating device is proposed. The heat-dissipating device including a heat sink and a plurality of connecting bumps attached to connecting pads formed on the heat sink is mounted on a substrate by reflowing the connecting bumps to ball pads of the substrate. The connecting bumps and the ball pads help buffer a clamping force generated during the molding process, so as to prevent a packaged semiconductor chip from being cracked. Moreover, the reflowing process allows the connecting bumps to be self-aligned on the substrate, so as to assure the toning and planarity of the heat sink mounted thereon. Accordingly, during molding, the precisely-positioned beat sink can have its upper side closely abutting an upper mold, allowing a molding resin to be prevented from flashing on the upper side thereof i.e.

Abstract: A new flip-chip technology, denominated as DDFC (Direct-Downset Flip-Chip) technology, is characterized by the forming of a downset device hole in the substrate, and by the use of an array of solder bumps over the semiconductor chip and an array of recessed solder-bump pads of an inwardly-tapered conical shape over the bottom surface of the device hole for bonding the semiconductor chip to the substrate. During assembly, the semiconductor chip is embedded in a direct-downset manner into the device hole of the substrate, with the solder bumps being fitted and wetted to the recessed solder-bump pads. The proposed DDFC technology can be implemented without requiring solder-deflux or flip-chip underfill processes, thereby simplifying overall package fabrication.

Abstract: A semiconductor package structure with a heat-dissipation stiffener and a method of fabricating the same are proposed. The proposed packaging technology includes a substrate; a thermally-conductive stiffener mounted over the front surface of the substrate, the stiffener being formed with a centrally-hollowed portion and an outward-extending passage a semiconductor chip mounted on the front surface of the substrate and within the centrally-hollowed portion of the stiffener; an underfill layer filled and cured in a gap between the semiconductor chip and the substrate; and a plurality of solder balls mounted on the back surface of the substrate. Alternatively, the passage can be formed in the front surface of the substrate. During fabrication process, the passage is used for the injection of a cleaning solvent into the gap between the semiconductor chip and the substrate so as to clean away remnant solder flux.

Abstract: Bidirectional optical communication devices are attached to both ends of an optical fiber, and each of them has a transmitting light wave guide coupled to a semiconductor laser and a received light wave guide which is coupled to a photodiode, and optically separated from the transmitting light wave guide. On the end face of the light-incident area of the optical fiber on which transmitting light coupled to the optical fiber from the transmitting light wave guide is directed, the light axis of the transmitting light is set so as to tilt with respect to the normal to the end face of the light-incident area so as to prevent reflected light on the end face of the light-incident area caused by the transmitting light from entering the photodiode installed on the same side as the semiconductor laser.

Abstract: A multi-chip semiconductor package with a heat dissipating structure is proposed, in which a chip receiving cavity and an opening respectively formed in the heat dissipating structure and a chip carrier, are used to accommodate semiconductor chips therein with the chips being in direct contact with the heat dissipating structure, allowing heat generated by the chips to be rapidly dissipated through the heat dissipating structure. With the provision of through holes for interconnecting the chip receiving cavity and opening, gold wires pass the through holes and electrically connect the chips to the chip carrier. Such a structure with chips embedded in the chip receiving cavity and opening makes internal elements to be more compactly arranged in the semiconductor package, which is preferable in response to profile miniaturization of electronic product development.

Abstract: Method of processing photographs in a photographic laboratory by means of a photographic processing system, comprising the steps of: receiving customer orders and processing information, respectively assigned to the customer orders, each order comprising at least one photographic image and each processing information defining processing tasks, wherein a number of processing tasks is assigned to at least one processing site based on the processing skills of a number of operators available at the processing site, and if particular processing information of said received processing information, which is assigned to a corresponding order, requires the execution of at least one of said assigned processing tasks, the corresponding order is processed at the at least one assigned processing site for said execution.

Abstract: A flip-chip underfill method is proposed for the purpose of underfilling a gap formed beneath a semiconductor chip mounted in a flip-chip manner over an underlying surface. The flip-chip underfill method comprises the following procedural steps of: preparing a dispensing needle having an outlet; then, moving the dispensing needle in such a manner as to position the outlet thereof at a corner point between the upper surface and the sidewall of the semiconductor chip; and finally injecting resin at the targeted corner point, which allows the injected resin from the outlet of the dispensing needle to flow down along the sidewall of the semiconductor chip to the edge of the lower surface of the semiconductor chip and subsequently fill into the gap through capillary action.

Abstract: A multi-hip semiconductor package is proposed, in which a first chip and a second chip are mounted on opposing surfaces of a lead frame in a staggered manner. This staggered arrangement assures the die bonding quality for firmly disposing the second chip in the semiconductor package without being detrimental affected by the first chip. Moreover, as both opposing surfaces of the lead frame have chips mounted thereon, a mold flow of a molding resin used in a molding process can be balanced, so that turbulence the mold flow is decreased, and void formation can be avoided. In addition, the semiconductor package can incorporate a third chip in a stacked manner with respect to the first or second chip. This therefore further improves the functionality and performance of the semiconductor package.

Abstract: A liquid crystal display device having a touch panel that exploits a shutter effect of a liquid crystal layer includes an antiglare film placed behind the touch panel as seen by the viewer. The antiglare film fulfills the following three conditions: 0.3<Ra≦0.4; 50<Sm≦80; and 5≦H≦20; where Ra represents the center-line mean roughness (&mgr;m) of the surface of the antiglare film, Sm represents the irregularity interval (&mgr;m) of the surface, and H represents the haze value (%).

Abstract: A flip-chip packaging process is proposed, which can help assure reliable electrical bonding between chip-side solder bumps and substrate-side bond pads without being made open-circuited by the electrically-insulative material being used for flip chip underfill. The proposed flip-chip packaging process is of the type utilizing a no-flow underfill technique to prevent short-circuiting between neighboring solder bumps, and is characterized in the fabrication of electrically-conductive sharp-pointed studs over substrate-side bond pads to prevent open-circuiting between chip-side solder bumps and substrate-side bond pads.