Abstract: A BGA (Ball Grid Array) package fabrication method is proposed for the purpose of achieving solder ball coplanarity on a warped BGA package, such as a concavely-warped BGA package or a convexly-warped BGA package. The proposed method is characterized in the provision of a plurality of variably-sized solder-ball pads over the bottom surface of the substrate, each solder-ball pad having a specified size predetermined in accordance with pre-measured package warpage and predetermined relation of solder ball height against pad size. This provision allows the use of a solder mask having fixed-size openings, as contrary to the prior art that uses a solder mask having variably-sized openings, to allow the implanted solder balls to achieve coplanarity and have strengthened shear for robust solder joint.

Abstract: A new semiconductor packaging technology is proposed for the fabrication of a semiconductor package based on window pad type of leadframe. The proposed semiconductor packaging technology is characterized by the mounting of a window shim having a solid ring portion and a hollowed window portion over the die pad of the leadframe. The window shim is dimensioned in such a manner that the width of the ring portion thereof is larger than the width of the window portion of the die pad of the leadframe, while the width of the window portion of the window shim is smaller than the width of the semiconductor chip. This feature allows one design of the window pad type of leadframe to be universally suited for packaging semiconductor chips of various sizes. Moreover, the incorporation of the window shim additionally allows an increase in the heat-dissipation efficiency of the packaged chip.

Abstract: A wire-bonded semiconductor device with an improved wire-arrangement scheme is proposed, which can help minimize abnormal wire sweep during encapsulation process. Among the bonding wires on the semiconductor device, those located in corners would be mostly susceptible to abnormal wire sweep, particularly a high-loop bonding wire that is located in immediate adjacency to a low-loop bonding wire located in one corner of the wire-bonded semiconductor device. To solve this problem, the low-loop bonding wire that is located in immediate adjacency to the sweep-susceptible high-loop bonding wire is erected substantially to the same loop height as the high-loop bonding wire, so that it can serve as a shield to the sweep-susceptible high-loop bonding wire against the flow of injected resin during encapsulation process, thus preventing abnormal wire sweep.

Abstract: A BGA semiconductor package having an embedded heat sink is proposed. The heat sink mounted on a substrate includes a flat portion and supporting members for supporting the flat portion to be positioned above a semiconductor chip. The flat portion is formed with at least one taper air vent for ventilating air in a gap between the flat portion and the chip during a molding process. This further helps prevent voids from forming in an encapsulant due to the air trapped in a molding resin as being flowing slowly through the gap, and avoid the occurrence of a popcorn effect on the encapsulant during a temperature cycle in subsequent processes. As a result, quality and yield for the packaged products can be significantly improved.

Abstract: A lead-frame-based chip-scale package (CSP) structure and a method of manufacturing the same are proposed. The proposed CSP structure is characterized in the use of a specially-designed lead frame having an inner-lead part and an outer-lead part, which each inner lead being formed with a deformed portion. During the encapsulation process, an epoxy molding compound (EMC) is formed to encapsulate the semiconductor die and the inner-lead part. By the proposed CSP structure, both sides of the inner-lead part can be wrapped by the EMC due to it being raised by the deformed portion to within the EMC. As a result, during the lead-singulation process, the inner-lead part can be firmly supported in position, thereby reducing the occurrence of micro cracks in the EMC above the inner-lead part that would otherwise occur in the prior art.

Abstract: Disclosed is a semiconductor package which has no resinous flash formed on lead frame and its manufacturing method.

Abstract: A BGA (Ball-Grid Array) integrated circuit package is proposed, which is incorporated with a palladium-coated heat-dissipation device to help enhance the thermal conductivity of the integrated circuit package and make the manufacture more cost-effective to implement. The heat-dissipation device includes a base block made of heat-conductive material and a palladium layer coated over the surface of the base block. The palladium-coated base block is formed into a predefined shape having a surface exposed to the outside of an encapsulant encapsulating an integrated circuit chip of the BGA integrated circuit package. The palladium coating can help protect the exposed surface of the heat-dissipation device against oxidation and also prevent the delamination from occurrence and the marking ink from erasure. The manufacture of the BGA integrated circuit package structure is therefore more ensured in quality and more cost-effective to implement.

Abstract: A method for protecting a specific region in the sample applied in preparing an ultra-thin specimen is disclosed. The method includes the steps of (a) forming a first concavity on a first side of the specific region by a focus ion beam (FIB) technique, (b) forming a second concavity on a second side of the specific region opposite to the first side by the focus ion beam technique, (c) filling the first concavity and the second concavity with a first metallic packing and a second metallic packing respectively, and (d) forming a third metallic packing on the specific region and extending to connecting with the first metallic packing and the second metallic packing to define a protecting device for protecting the specific region.

Abstract: There may be used a film-forming apparatus having a substrate 4 that is rotatable around the center of one rotating axis 10 in the vertical direction situated in an inner cylinder 12, and a plurality (four in FIG. 2) of target units each comprising the pair of targets 2A, 2B (2B is under 2A serially arranged in the vertical direction inside an outer cylinder 13 opposite the surface 4a of the substrate 4, which are arranged in parallel in the circumferential direction of the inner wall of the outer cylinder 13. By employing a method whereby voltage is applied while alternatively reversing the polarity to each of the targets 2A, 2B, it is possible to form a coating on the surface of a substrate by glow discharge sputtering, to accomplish destaticizing while the sputtering can be carried out using a small in-line or bell jar apparatus with small space.

Abstract: A flip-chip bonding structure on substrate for flip-chip package application is proposed, on which solder bumps can be bonded for electrically coupling a flip chip to the substrate. The proposed flip-chip bonding structure is characterized in that its solder-bump pads can be dimensionally-invariable irrespective of a positional deviation in solder mask due to misalignment. Moreover, the proposed flip-chip bonding structure can help allow each attached solder bump to be reduced in horizontal extent as compared to the prior art, so that neighboring solder bumps would be less likely short-circuited to each other and flip-chip underfill can be more easily implemented.

Abstract: A control unit is arranged for a synchronous motor formed of a rotor provided with a magnet. The control unit includes a 180°-conduction drive unit for performing 180°-conduction drive of the synchronous motor, a 120°-conduction drive unit for performing 120°-conduction drive of the synchronous motor, a rotation speed calculating unit for calculating the motor rotation speed, a rotation-speed-vs.-efficiency table unit storing an efficiency relative to a rotation speed of the motor, and a drive method selecting unit for selecting an optimum drive method for the current rotation speed based on the current rotation speed and information stored in the rotation-speed-vs.-efficiency table unit. Thereby, the synchronous motor performs 120°- or 180°-conduction drive in accordance with the current rotation speed to achieve the drive with an optimum efficiency.

Abstract: The present invention relates to a semiconductor package with a heat sink. There is at least one chip adhered to the substrate and the heat sink is constituted by a planar plate and a support for supporting the planar plate to a height for positioning the planar plate above the chip. The planar plate has a top surface exposed outside a resin body used for encapsulating the chip and the heat sink, and a bottom surface opposed to the top surface. The planar plate further has a thick portion formed on the bottom surface relative to the position of the chip, wherein there is a gap formed between the end surface of the thick portion and the chip to prevent the heat sink from directly contacting with the chip, and an end surface of the thick portion has a plurality of flow channels formed along the flowing direction of the molding gate to avoid the formation of void in the gap so as to increase the yield rate of products.

Abstract: A flip-chip package technology is proposed for use to fabricate a dual-chip integrated circuit package that includes two semiconductor chips in a single package unit, which is characterized in the forming of a flash-barrier structure that can help prevent the underfill material used in flip-chip underfill process from flashing to other unintended areas. The flash-barrier structure can be either a protruded dam structure over the underlying semiconductor chip, or a groove in a coating layer formed over the underlying semiconductor chip. During flip-chip underfill process, the flash-barrier structure can confine the underfill material within the intended area and prevent the underfill material from flowing to other unintended areas such as nearby bonding pads, so that the finished package product can be assured in quality and reliability.

Abstract: A method is proposed for the fabrication of plated circuit lines, including contact fingers, electrically-conductive traces, and solder-ball pads, over an BGA (Ball Grid Array) substrate. The method is characterized by that contact fingers, electrically-conductive traces, and solder-ball pads on the BGA substrate are interconnected with provisional bridging lines; and then, each integrally-connected group of the contact fingers, the electrically-conductive traces, and the solder-ball pads is connected via a branched plating line to a common plating bus. During plating process, the plating electrical current can be applied to the plating bus and then distributed over these branched plating lines to all of the contact fingers and the solder-ball pads. Finally, a drilling process is performed to break all the provisional bridging lines into open-circuited state.

Abstract: A flip-chip bonding structure with stress-buffering property is proposed, which can help prevent cracking and warpage to the flip-chip construction due to thermal stress. The proposed flip-chip bonding structure used to bond a flip chip to a substrate, and is characterized in the provision of a first electrically-conductive stress-buffering layer over the chip-side bond pad and a second electrically-conductive stress-buffering layer over the substrate-side bond pad, so that under high-temperature conditions, the thermal stress from the flip chip can be buffered by the first electrically-conductive stress-buffering layer, while the thermal stress from the substrate can be buffered by the second electrically-conductive stress-buffering layer, thus preventing cracking and warpage to the flip-chip construction. As a result, the finished flip-chip package can be more assured in quality and reliability than the prior art.

Abstract: A leadframe with a dot array of silver-plated regions on die pad is proposed, which is designed specifically for use in the construction of an exposed-pad type of semiconductor package. The proposed leadframe is characterized by that the front side of the die pad is partitioned into a centrally-located die-mounting area and a peripherally-located ground-wire bonding area; and wherein the die-mounting area is selectively silver-plated to form a dot array of silver-plated regions, while the peripheral area of the die pad is entirely silver-plated to form a silver-plated peripheral area. In addition, the die-mounting area of the die pad can be further formed with a plurality of dimples for the purpose of increasing the contact area between the die pad and a silver-epoxy layer that is to be pasted over the die-mounting area for use to adhere a semiconductor chip to the die pad.

Abstract: A semiconductor package structure with exposed die pad is proposed. The proposed package structure comprises a lead frame having a die pad and a plurality of leads, with the bottom surface being formed with a cutaway portion at the peripheral edge thereof; a semiconductor chip mounted on the front surface of the die pad and electrically coupled to the leads; and an encapsulation body for encapsulating the semiconductor chip and part of the leads, with the bottom surface of the die pad being exposed to the outside of the encapsulation body.

Abstract: An audio compact disc title with a high density format adapted to be used in a compact disc player is disclosed. The audio compact disc title includes a plurality of tracks, each of the tracks has a plurality of audio sectors for storing audio data, wherein the audio data are divided into a plurality of audio signals alternately stored in the audio sectors, and a compact disc identifying code for representing the relatively high density format of the audio compact disc title for the compact disc player. A method for recording audio data in an audio compact disc title with a high density format is also disclosed. The method includes steps of dividing the audio data into a plurality of audio signals, rearranging the plurality of audio signals to space any two continuous audio signals by other audio signals, and recording the rearranged audio signals in the audio compact disc title.

Abstract: An underfill method is proposed for performing flip-chip underfill in an integrated circuit package of the type based on a WBCOCBGA (Wire-Bonded Chip-On-Chip Ball-Grid Array) construction which includes two semiconductor chips arranged in a chip-on-chip (COC) manner, wherein the underlying chip is electrically coupled to the substrate by means of wire bonding (WB), while the overlying chip is mounted in a flip-chip manner over the underlying chip and electrically coupled to the same by means of ball grid array (BGA) technology. The proposed method is characterized in the forming of an elongated dam structure over a preserved side surface area of the underlying chip beside the bonding wires connected to the underlying chip. During the dispensing process, the dispensed resin can fill into the gap under the overlying chip through capillary action while being prevented from coming in touch with the nearby bonding wires by the dam structure.

Abstract: This invention discloses a flame retarding thermoplastic resin composition, which is comprised of (i) a thermoplastic resin and (ii) a phenolic resin compound as a flame retardant, wherein the phenolic resin compound contains a nitrogen-containing heterocycle and phosphorus. Since the flame retarding thermoplastic resin composition of this invention does not contain halogen, and has excellent flame retardant properties and high heat resistance, it is useful in producing parts and products in the fields of electronics, electricity and automobile.