Abstract: A semiconductor device package structure is proposed, which allows the encapsulation body to be highly secured in position to the leads, making the encapsulation body hardly delaminated from the leads. The proposed semiconductor device package structure comprises a die pad; a semiconductor chip mounted on the die pad; a plurality of leads arranged around the die pad, each lead being formed with a bolting hole; a plurality of bonding wires for electrically coupling the semiconductor chip to the leads; and an encapsulation body which encapsulates the semiconductor chip and the bonding wires and includes a part filled in the bolting hole in each of the leads. The bolting hole is characterized in the forming of a constricted middle part or an inclined orientation with respect to the lead surface, which allows the encapsulation body to be highly secured in position to the leads, thereby making the encapsulation body hardly delaminated from the leads.

Abstract: A substrate of a semiconductor package is proposed, which is formed with a strip copper layer on a core layer of the substrate, wherein a solder mask is arranged to cover the core layer and two lengthwise sides of the copper layer by a width between 0.1 mm to 1.0 mm, while a surface between the sides of the copper layer is exposed by forming a groove opening to the atmosphere and plated with gold. This makes bulges generated by shrinkage of the solder mask covering the sides of the copper layer extend outwardly in a direction away from the groove opening, allowing clamping force to be sufficiently exerted on the substrate by a mold during an encapsulation process. As such, after completing the encapsulation process, an encapsulating resin remained in the runner can be easily removed without damaging the substrate, and also resin flash can be prevented from occurrence.

Abstract: A layout method is proposed for semiconductor package substrate with plating bus, such as TFBGA (Thin & Fine Ball Grid Array) substrate, which can help allow each singulated package unit from the substrate to be substantially free of trace short-circuits due to misaligned cutting during singulation process. The proposed layout method is characterized in the provision of a plating bus of a special layout pattern for interconnecting all the via lands alongside each singulation line. The plating bus includes a plurality of crosswise segments, each being used to to interconnect one crosswise-opposite pair of the via lands across the singulation line; and a plurality of diagonal segments, each being used to interconnect one neighboring pair of the crosswise segments diagonally to each other across the singulation line. The proposed layout method allows each singulated package unit from the substrate to be substantially free of trace short-circuits due to misaligned cutting during singulation process.

Abstract: A dual-die packaging technology is proposed to pack two semiconductor chips in one single package module, so that one single package module is capable of offering a doubled level of functionality or data storage capacity. The proposed dual-die packaging technology is characterized in the use of a face-to-face stacked dual-die construction to pack two integrated circuit chips, such as flash memory chips, in one single package module. The first semiconductor die has its non-circuit surface attached to the front side of the die pad of the leadframe, while the second semiconductor die has its circuit surface attached by means of adhesive layer to the circuit surface of the first semiconductor die, thus forming a face-to-face stacked dual-die construction over the die pad of the leadframe, allowing one single package module to offer a doubled level of functionality or data storage capacity.

Abstract: A semiconductor package with a heat dissipating structure is proposed, in which the heat dissipating structure is precisely positioned on a substrate, in a manner that a plurality of solder balls self-align with ball pads formed on the substrate, and support a heat sink to be positioned above a semiconductor chip mounted on the substrate. This therefore makes the heat sink closely abut a molding cavity of an encapsulating mold in a molding process, and prevents resin flash from occurring on the heat sink, so that a surface of the heat sink can be directly exposed to the atmosphere for improving heat dissipating efficiency. Moreover, the solder balls characterized in softness deform in response to a pressure generated by the encapsulating mold during molding. Therefore, the substrate can be protected from being damaged by the pressure, and thus quality of the semiconductor package can be assured.

Abstract: A computer coupling device is provided for coupling together two computer systems, such as a notebook computer and a desktop computer, to allow each computer to share the system resources of the other computer and to allow the two computer systems to perform dual-CPU parallel processing. When the notebook computer wants to gain access to the system resources of the desktop computer, the computer coupling device connects the host bus and the PCI bus of the notebook computer respectively to the host bus and the PCI bus of the desktop computer. Alternatively, when parallel processing is required, the computer coupling device connects the CPU of the notebook computer to the CPU of the desktop computer to allow the two CPUs to exchange data during dual-CPU parallel processing.

Abstract: A new semiconductor packaging technology is proposed for the fabrication of a thermally-enhanced stacked-die BGA (Ball Grid Array) semiconductor package. By the proposed semiconductor packaging technology, a substrate is used as a chip carrier for the mounting of two semiconductor chips in conjunction with a heat spreader thereon, wherein the first semiconductor chip is mounted over the substrate through flip-chip (FC) technology; the heat spreader is mounted over the first semiconductor chip and supported on he substrate; and the second semiconductor chip is mounted on the heat spreader and electrically coupled to the substrate through wire-bonding (WB) technology. To facilitate the wire-bonding process, the heat spreader is formed with a plurality of wire-routing openings to allow the bonding wires to be routed therethrough. Since chip-produced beat during operation can be dissipated through the heat spreader, it allows an enhanced heat-dissipation efficiency.

Abstract: A terminal apparatus is constituted by an added data input section, a writing start/completion detecting section, an input position detecting section, a connected terminal selecting section, a specific terminal information input section, an added data storing section, a specific terminal information storing section, a specific terminal judging section, a display section, a transmitting terminal identification information adding section, a transmitting terminal information storing section, a transmitting terminal judging section, a data transmitting section, a data receiving section, a memory section(not shown), and a section(not shown) for inputting and measuring date information. This arrangement allows an information processing apparatus, which sends and receives data to and from a plurality of information processing apparatuses via a communicating means and includes a common board for a plurality of information processings, to improve ability to recognize data.

Abstract: A TBGA (Tape Ball Grid Array) package assembly with grounded heat sink and method of fabricating the same is provided, which is constructed of a tape, a heat sink, and at least one semiconductor chip. The proposed TBGA technology is characterized by that a grounding plug is formed by first forming a via hole in the heat sink and a via hole in the tape without penetrating through the grounding solder-ball pad, and then filling an electrically-conductive material, such as solder or silver paste, into the heat-sink via hole from the top of the package assembly until filling up the tape via hole and the heat-sink via hole. As the semiconductor chip is mounted in position, its grounding pads are electrically bonded to the heat sink, thereby allowing the semiconductor chip to be externally grounded through the grounding plug, the grounding solder-ball pad, and the solder ball attached to the grounding solder-ball pad.

Abstract: An integrated-circuit package with a quick-to-count finger layout design on substrate is proposed, which can help fabrication engineers to visually check the total number of fingers on the substrate in a quick and accurate manner. The proposed integrated-circuit package is characterized by the provision of a line-up array of fingers which includes a plurality of first-shape fingers partitioned equally in number into a plurality of subgroups; and a plurality of second-shape fingers, which are substantially visually distinguishable in outer appearance from the first-shape fingers, and which are interposed between adjacent subgroups of the first-shape fingers to serve as count tokens. This finger layout design allows the fabrication engineers to visually check the total number of the line-up array of fingers on the substrate simply by counting through the second-shape fingers that serve as count tokens and then multiply the result by the number of first-shape fingers in each subgroup plus one.

Abstract: A stacked dual-chip semiconductor packaging technology is proposed for the packaging of two semiconductor chips in one single package unit. The proposed dual-chip semiconductor package is characterized by an intercrossedly-stacked dual-chip arrangement which is constructed on a specially-designed leadframe having a supporting frame; a die pad supported on the supporting frame and having a peripheral-located upper portion and a centrally-located downset portion; and a set of leads linked to the supporting frame and arranged around the die pad. By the proposed packaging technology, a first semiconductor chip is mounted within the downset portion of the die pad, while a second semiconductor chip is mounted on the upper portion of the die pad in an intercrossedly-stacked manner in relation to the first semiconductor chip. Compared to the prior art, the propose technology allows the packaging process to be implemented in a less complex and more cost-effective manner.

Abstract: A semiconductor package is proposed, in which a lid is attached to a semiconductor chip and appropriately spaced apart from a heat sink having a top surface thereof exposed to the outside an encapsulant, so as to prevent external moisture from condensing on the semiconductor chip and reduce a thermal stress effect on the semiconductor chip. Moreover, a thermal conductive path is reduced in a portion passing through the encapsulant, allowing the heat-dissipating efficiency to be improved. In addition, with no contact between the heat sink and the semiconductor chip, quality of the semiconductor package is assured with no damage to the semiconductor chip.

Abstract: A flip chip semiconductor package is proposed, in which a dam structure is formed of an adhesive compound such as epoxy resin on a substrate around a chip. The adhesive compound has a larger coefficient of thermal expansion than that of the substrate, and generates a greater thermal contraction force for counteracting thermal stress of the substrate in a cooling process in fabrication, so as to maintain planarity and structural intactness of the substrate and chip. Moreover, the chip can be made in a manner as to expose a non-active surface thereof to the atmosphere for facilitating dissipation of heat generated by the chip, while a heat sink can be additionally disposed on the chip, so as to further improve heat dissipating efficiency of the semiconductor package.

Abstract: A fabricating method for a semiconductor package is proposed, in which a substrate module plate consisting of a plurality of array-arranged substrates is mounted with at least one chip on each of the substrates, so as to allow a heat sink module plate coated with an interface layer to attach to the chips. Subsequently, an encapsulant is formed by a molding compound for encapsulating the chip carrier module plate, the chips and the heat sink module plate during molding. As the adhesion between the interface layer and the encapsulant is smaller than that between the heat sink module plate and the encapsulant, the portion of the encapsulant formed on the interface layer can be easily removed without causing damage to the fabricated semiconductor package and delamination of the heat sink module plant from the encapsulant.

Abstract: A modified SMT (Surface Mount Technology) process is proposed for mounting an exposed-pad type of semiconductor device over a PCB (printed circuit board), which can help prevent the problem of floated soldering of the semiconductor device over the PCB. By this modified SMT process, a plurality of via holes are formed in the pad-mounting area of the printed circuit board; and a solder material is pasted over the bottom end of each of the via holes. As the semiconductor device is mounted in position over the printed circuit board, a solder-reflow process is performed on the pasted solder material so as to cause the pasted solder material to be wetted to the entire surface of the solder-wettable layer in each of the via holes, thereby allowing the solder material to reflow to the upper end of each of the via holes where the reflowed solder is also wetted to the exposed die pad of the semiconductor device, thereby securely bonding the semiconductor device to the PCB.

Abstract: An integrated circuit package having an encapsulating body with a flanged portion and an encapsulating mold for molding the encapsulating body are proposed. It is a characteristic feature of the proposed encapsulating mold that the encapsulating-body cavity formed in the upper mold further includes a constricted cutaway portion in the rim thereof. The constricted cutaway portion can be either uniform in thickness or formed in a multi-step staircase-like shape. During the molding process, the resin used to form the encapsulating body would flow into this constricted cutaway portion; and within the constricted cutaway portion, the resin would more quickly absorb the heat of the upper mold, thus increasing its viscosity and retarding its flowing speed. As a result, the resin would less likely to flash onto those surface parts of the substrate beyond the encapsulating body.

Abstract: An acoustic diaphragm arranged to face a driving device of a loudspeaker is disclosed. The acoustic diaphragm comprises at least one laminated structure, one of which includes a first carbon fiber layer, a glue layer formed on the first carbon fiber layer, and a second carbon fiber layer formed on the glue layer. The acoustic diaphragm of the present invention has small distortion of sound, less deformation by external force, better stereo, and sound quality, as compared with a conventional diaphragm.

Abstract: A method of fabricating a FCBGA (Flip-Chip Bal-Grid-Array) package with molded underfill is proposed, which is characterized by the forming of a mold-buffering opening in the solder mask at the exit of the vent hole in the substrate, wherein the mold-buffering opening is dimensioned to be greater in width than the inside diameter of the vent hole, so that during molding process when the encapsulation material infiltrates to the exit of the vent hole, it can be confined within the mold-buffering opening, thereby preventing it from flashing to nearby solder-ball pads. Since there would substantially exist no mold flash over the exposed surface of the solder mask and the solder-ball pads, the resulted FCBGA package would be assured in the quality of its outer appearance and the bonding between the solder-ball pads and the subsequently attached solder balls thereon.

Abstract: A BGA (Ball Grid Array) package is proposed, which is characterized by the provision of an interdigitated power/ground ring layout scheme. By this layout scheme, the power ring and the ground ring are each formed with a line portion and a plurality of toothed portions; with the toothed portions of the power ring being are interdigitated with the toothed portions of the ground ring. Moreover, the power/ground vias are all connected to the toothed portions of the power ring and the ground ring, thereby leaving the line portions of the power ring and the ground ring unoccupied by the power/ground vias, allowing the routability of power/ground wires to be higher than the prior art. Moreover, solder bask is formed in such a manner as to cover all the toothed portions of the ground ring, so that power wires can be prevented from being short-circuited to the ground ring due to sagging.

Abstract: The present invention relates to apparatus and method for forming a proteinaceous emulsion or batter into shaped food products such as sausages without the use of a casing. A supply of suitable proteinaceous emulsion is provided and such emulsion is conveyed under pressure into an elongated hollow stuffing tube to form a continuous length of shaped emulsion. Thereafter the shaped emulsion is directed into a molding tube which is slideably mounted about the stuffing tube. As the emulsion enters the molding tube, the pressure of the emulsion causes the molding tube to move away from the stuffing tube. A treating fluid, such as a diluted food grade acid, is directed to the interior surface of the molding tube at about the point where the emulsion first enters the molding tube. The treating fluid is directed to the interior of the molding tube in such a manner that the interior of the molding tube is continuously wetted by the treating fluid as the molding tube moves relative to the stuffing tube.