Abstract: Techniques for applying attenuation to audio signal frames in MPEG and similar compression systems are described, together with a method for mixing such signals without decompression. Each entry in a data frame (F) has an associated scale-factor index (SF), identifying a respective entry in a sequentially arranged and spaced table of scale-factor values. The attenuation technique (20), which suitably precedes mixing for at least one channel involves simple addition to scale factor index values to refer to a different scale-factor value. Respective sub-band data groups from each channel are compared in terms of their respective scale factors and following scaling the data for the two groups is added together. The scale-factor table spacing, which suitable corresponds to a 1 dB attenuation, is used for quick scaling of the results of the addition if overflow is determined to have occurred.

Abstract: An electronic circuit comprises coupled transconductors (TR1 and TR2). The transconductors comprise two complementary differential pairs whose outputs are connected directly to two output terminals. Two diodes (P3, N3) are arranged in series between the common terminals of the differential pairs. The common-mode voltage of the differential pairs is available on the node between the two diodes. The common-mode voltage of the one transconductor (TR2) is used to control one of the bias current sources of the other transconductor (TR1) and, if desired, also that of the one transconductor (TR2). In this way the common-mode voltage on the output terminals of the other transconductor (TR1) is fixed.

Abstract: A method of manufacturing semiconductor devices whereby first a Ti layer (8) and then a TiN layer (9) are deposited on slices of semiconductor material (20). The slices are placed on a support (30) one after the other in a deposition chamber (22), the support being positioned opposite a target of Ti (32) surrounded by an annular anode (31). Material is then sputtered off the target by means of a plasma (35) generated near the target. The plasma is generated in Ar during deposition of the Ti layer and in a gas mixture of Ar and N.sub.2 during deposition of the TiN layer. After the deposition of the TiN layer, before a next slice is placed in the chamber each time, the target is cleaned during an additional process step in that material is sputtered off the target by means of a plasma generated in Ar. The additional process step is ended the moment the target has regained a clean Ti surface again.

Abstract: An array reading or addressing circuit which enables the signals stored in an array of electrical elements to be individually read and which reduces the number of connections to the array of electrical elements. The circuit includes a plurality of terminals 32, each terminal being connected to a signal reading device 30 or address signal generating device 31 through a respective switch S. The elements 12 of the array are each connected to a unique combination of the terminals, and when a combination of switches S are in a conducting state, electrical signals of a combination of electrical elements are fed to the signal reading device 30, or addressed by the address signal. The output signals for different switch combinations, which each represent combinations of pixel values, are processed to enable the signal from each electrical element to be determined.

Abstract: In charge-coupled imaging devices it is generally necessary to provide zones (12) in the matrix with a contact. These zones may form part, for example, of a mechanism for draining charge, for example as a protection against overexposure. In the case of imaging devices with a horizontal readout register on one side of the matrix, these contacts can be provided on the opposite side. However, it is often desirable or even necessary, as in the case of imaging devices with four-quadrant readout, to provide such contacts on the same side as the horizontal readout register. To this end, a dummy line (14'-17') is provided in accordance with the invention between the matrix and the horizontal readout register (6), said dummy line having an electrode structure which leaves room for contact windows (22) to the zones (12).

Abstract: A high frequency analog-to-digital converter in which a memory stage receives the result of a series of comparisons of an analog input voltage Vin with a set of reference voltages Vi (where i=0 to Q). Each memory cell Mi (where i=0 to Q) comprises N memory flip-flops L0, L1, . . . LN-1, a multiplexer Mx, and a logic or control module CL. All of the data inputs of the memory flip-flops L0, L1, . . . LN-1 are connected together to the data input of the memory cell. The jth memory flip-flop (where j=0 to N-1) receives at its clock input the clock signal which has been delayed by means of a delay cell having a delay of j.T/N, where T is the period of the clock signal. The data outputs of the N memory flip-flops are connected to the N data inputs of the multiplexer, whose P control inputs receive the P outputs of the control module so that the multiplexer supplies the output signal of the jth memory flip-flop Lj at its output during each (j+1)th fraction of the period T/N.

Abstract: The invention relates to a method of manufacturing a varicap diode whereby a silicon substrate with an epitaxial layer of a first conductivity type is provided with a first zone through the provision of dopant atoms of a first conductivity type in the epitaxial layer and is provided with a second zone adjoining a surface of the epitaxial layer through the provision of dopant atoms of a second conductivity type opposed to the first in the epitaxial layer, a pn junction being formed between the second zone and the first zone. According to the invention, the method is characterized in that the second zone is provided in that a layer of polycrystalline silicon provided with dopant atoms of the second conductivity type is provided on the surface, and in that the dopant atoms are diffused from this layer into the epitaxial layer, whereby a pn junction is formed at a distance of less than 0.3 .mu.m from the polycrystalline silicon.

Abstract: The invention entails a circuit that enables maximum headroom cascode biasing schemes to locally generate all the required voltage from a single reference current. This leads to a considerable die size reduction compared to existing circuits, which require two reference currents. Single reference current biasing is achieved by a start-up circuit that overcomes the zero-current steady-state bias solution that would normally occur when attempting to bias a maximum headroom CMOS cascode biasing schemes from a single input current. The start-up circuit is extremely simple and does not counteract the die area advantage of the biasing set-up, nor does it affect its other virtues, including high isolation from one current source to another and robustness against lot-to-lot process variations.

Abstract: A high-frequency power amplifier circuit offers the advantages of high input impedance, good linearity, high power efficiency and accurate bias current control in a compact and economical circuit configuration. The amplifier includes a single-ended output stage driven by a symmetrical push-pull emitter follower stage with both active pull-down and active pull-up capability. The emitter follower stage is driven by an active phase-splitter stage, with bias current for the phase-splitter stage and subsequent stages being provided by a bias-current control stage which is directly connected to the phase splitter stage. A linear voltage-to-current converter stage receives a high-frequency input voltage and provides a high-frequency current signal to the input terminal of the bias-current control stage that controls the current in the output stage.

Abstract: In a trap circuit of the bridged-T type, having a delta RC circuit (RR, C1, C2) and a parallel resonant circuit (L, Cp), the capacitance Cp is constituted by variable capacitance diodes (D1, D2) connected via a resistor (8) to a control voltage (Vtone), and the resistor (RR) of the bridged-T circuit is constituted by a PIN diode whose current is controlled by the same control voltage (Vtone) via a resistor (9).

Abstract: In a gain control circuit (GCC), a plurality of parallel-arranged differential pairs (DP1,DP2 . . . DPN) is unbalanced as a function of a gain control signal (Vagc). Furthermore, the gain of individual differential pairs (DP1,DP2 . . . DPN) is reduced when the unbalance is increased, and vice versa. Accordingly, a favorable performance in terms of noise and distortion can be obtained.

Abstract: An IF demodulator circuit with IF gain control at a variable time constant, which receives an IF carrier including synchronizing pulses, a black porch and picture information with a positively modulated picture signal, in which the IF picture signal is amplified to a nominal amplitude value by the gain control, and which includes an IF demodulator (3) which demodulates the IF picture signal and supplies a picture signal from the output, while, for a gain control which is independent of DC offsets that may occur in the picture signal, the demodulator circuit is constructed in such a way that a black level detector (8) for generating a black level signal used as a threshold value signal in conformity with the amplitude value of the black porch of the picture signal supplied by the amplitude demodulator (3) is provided, that a DC offset circuit (4) is provided, which raises the DC component of the picture signal and/or lowers the DC component of the threshold value signal in such a way that both signals are offs

Abstract: An integrated optical circuit includes a first device and a second device, which devices are connected by a polarization convertor. The polarization convertor includes a curved section of a waveguide, integrated in the optical circuit. The curved section may have several differently curved subsections. The conversion ratio is determined in part by the radius of curvature of the curved subsections as well as by the number of transitions between subsections.

Abstract: A transmission system uses two channels (CHA, CHB). It includes a transmitting apparatus (1) having an input access (5) for receiving the information to be transmitted, output accesses (7A, 7B) connected to the channels for broadcasting the information to be transmitted, a first transmission delay element (8) associated to one of the accesses for delaying the information to be transmitted, a receiving apparatus (10) having accesses (11A, 11B) for receiving the information signals from the channels, a measuring circuit (15) for measuring the qualities of the various channels, and a network circuit (22) for selecting one of the channels.

Abstract: A mobile radio transceiver comprising a hands-free facility, which hands-free facility combines at least two acoustic input signals to produce an output signal, and an adaptive filter is provided for filtering the combined output signal. To achieve an improved speech quality, a high-pass filter is provided for filtering the acoustic input signals.

Abstract: In a folding A/D converter, a comparison part CPM provides a plurality of comparison signals Sc1 . . . Sc9 in response to an input signal Si. The transients in the comparison signals Sc1 . . . Sc9 are mutually shifted and substantially overlap. Because of the overlap, only a relatively small input signal variation is needed to pass all the transients. A limiting part LIM effectively selects portions of the transients. A combining part CBM effectively multiplexes these selected portions into a folding signal Sf. The selection by the limiting part LIM prevents distortion of the folding signal Sf, despite the overlap.

Abstract: An inductive structure for an integrated circuit. The inductor has a first turn that shields the other turns of the inductor from a proximate ground plane. Multiple turns are disposed one above another in respective metalization layers of the integrated circuit. The turns are partial loops and are electrically coupled end-to-end with vias. Predetermined ones of the turns have additional portions in different layers. An additional portion of a turn is an electrically conductive strip deposited above the turn in a higher metalization layer and electrically coupled to the turn, thereby increasing the surface area of the turn and decreasing resistance of the turn. A buried n-type loop disposed below the first turn and below the surface of the substrate shields the first turn from the capacitive effects of the substrate.

Abstract: Hard-open defects between logic gates of an address decoder and the voltage supply render a memory conditionally inoperative. The decoders are therefore examined for such hard-open defects. Two cells of two logically adjacent rows or columns are written with complementary logic data. If a Read operation reveals the data in the two cells to be identical, the presence and location of a hard-open defect in the decoders is demonstrated. Alternatively, the memory is provided with a fault-tolerant decoder that comprises additional disabling circuitry to properly disable the rows and columns even when a hard-open defect is present in the decoders' logic gates.

Abstract: A high-frequency power amplifier circuit offers the advantages of high input impedance, high power efficiency and accurate bias current control in a compact and economical circuit configuration. The amplifier includes a single-ended output stage driven by a symmetrical push-pull emitter follower stage with both active pull-down and active pull-up capability. The emitter follower stage is driven by an active phase-splitter stage, with bias current for the phase-splitter stage and subsequent stages being provided by a bias-current control stage which is isolated at high frequencies from the high-frequency input signal to the amplifier.

Abstract: A semiconductor device comprises a substrate (1) with a plane surface (4) on which a layer structure (2) is formed in a number of layers (5, 7, 9, 13, 15, 17). The side of the substrate on which the layer structure was formed is fastened to a plane support body (18) by means of a glue layer (19) which encompasses spacer elements (20). These spacer elements are fastened to the surface of the substrate and all have the same height measured from the surface (4). In fastening the substrate to the support body, glue is provided and the substrate is pressed onto the support body so that the pressure is evenly distributed over the spacer elements.