Abstract: The invention relates to a nozzle for a combustion device in which an improved flame shape is achieved in that a bundle comprising a plurality of small tubes is arranged in an outer tube.

Abstract: A device and method for controllably locally altering the magnetization direction in a body of magnetic material, whereby a layer of at least one of non-metallic material and a semi-metallic material is disposed on a surface of the body, on which layer is provided a body of magnetic material having a fixed magnetization direction, whereby both bodies of magnetic material are magnetically coupled across the interposed layer, the nature of this magnetic coupling being locally alterable by means of locally subjecting the layer to a controllable electric field.

Abstract: An optoelectronic semiconductor device with at least one laser and two mutually parallel, strip-shaped active regions, whose ends are optically coupled at one side, is a very suitable radiation source or amplifier, for example as a tunable radiation source. More than one kind of radiation is often present in such a device, whereas it is desirable for only one kind of radiation to pass through a gate of the device. To achieve this in prior devices, an additional component, such as a filter or isolator, is necessary.

Abstract: Receiver and transmission system for orthogonal frequency-division multiplexing signals comprising a frequency synchronization circuit (116) which has a local oscillator (214) whose frequency is controlled by a correction signal .epsilon.. The latter is generated by a frequency detector (213) which operates in the time domain, by utilizing the redundant information contained in such signals. The performance of the invention is particularly of interest for transmissions on multipath channels which occur in mobile radio, digital television, and so on.

Abstract: In an LCD or other electronic device, thin-film circuit elements on a substrate (100) form a sample-and-hold or other sampling circuit (10). The circuit (10) comprises a TFT (Ts) as a sampling transistor and preferably another TFT (T2) to compensate for displacement currents in charging and discharging the insulated gate (12) of the sampling TFT. Even when T2 is included, a slow drift in output voltage (Vo) is observed when Ts switches off, and this limits use of the circuit, especially in large area active-matrix devices. In accordance with the invention this slow drift is removed or significantly reduced by injecting minority carriers into the channel region of Ts (and T2) from a doped opposite-type region (119) or Schottky contact region (119) which is forward biased via a thin-film supply line (129). The minority carriers neutralise majority carriers which are being slowly released by thermal emission from trapping states in the TFT body.

Abstract: A noise-insensitive device for generating a bias current includes a reference voltage source for supplying a reference voltage between a first reference terminal and a second reference terminal. A bias current generator generates the bias current in response to the reference voltage and includes a first and-a second input terminal coupled to the first and the second reference terminal via connecting wires which receive the reference voltage. A first and a second transistor arranged as a differential pair with the gate of the first transistor coupled to the first input terminal and the gate of the second transistor coupled to the second input terminal. The source of the first transistor and the source of the second transistor are coupled to one another at a common terminal for receiving a common current. Each of said transistors has a drain for supplying a first transistor current and a second transistor current, respectively, whose difference decreases when the common current increases.

Abstract: A semiconductor body (2) has an active region (6) of n conductivity type formed of a material having a relatively low mass, high mobility conduction band main minimum and at least one relatively high mass, low mobility conduction band satellite minimum and an injector region (9) defining a potential barrier (P) to the flow of electrons into the active region (6) of a height such that, in operation of the device, electrons with sufficient energy to surmount the barrier (P) provided by the injector region (9) are emitted into the active region (6) with an energy comparable to that of the at least one relatively high mass, low mobility conduction band satellite minimum. An electron containing well region (10a, 10b) of a material different from that of the active region (6) and of the injector region (9) is provided between the injector region (9) and the active region (6) for inhibiting the spread of a depletion region into the active region (6) during operation of the device.

Abstract: For saving memory space, the use of a sophisticated compressor is to be preferred to a simple reduction of the sampling frequency. However, for very high compression rates the total number of calculations is such that the compressor would no longer be capable of following the timing with which the samples arrive. Particularly in the case of a telephone/recorder where sound messages are received in separate call elements of limited duration, the invention consists of finally compressing once again samples that one has not been able to compress in real time at a sufficiently high compression rate.

Abstract: A communication system including a switching system which comprises a switching unit and a control circuit. The control circuit comprises a transmitting-side signalling handler procedure (ASH) for managing the connection and for exchanging messages with other procedures, and a receiving-side signalling handler procedure (BSH) for managing the connection and for exchanging messages with other procedures. For providing optional external services, the switching unit is coupled to a service control system. Furthermore, the control circuit comprises an additional procedure (ZUSA) for exclusively exchanging messages with the transmitting-side and the receiving-side signalling handler procedures (ASH, BSH).

Abstract: Integrated circuits comprising an EEPROM require a large amount of time for testing, because the write time for a memory cell is very long. Notably the first test after manufacture, with the circuit still present on the wafer, is time consuming. The invention proposes a drastic reduction of the duration of the first test after manufacture by supplying a number of integrated circuits with a voltage in parallel and by providing each integrated circuit with an element whereby several block-wise write cycles for alternately "0" and "1" are executed in substantially autonomously and at the end of the first test step predetermined information is retained. This step is followed by a thermal treatment, after which the integrated circuits are individually contacted and first tested for information retention.

Abstract: The off-state leakage current, threshold voltage and on-state current of a thin-film transistor (TFT) can be degraded by operation at high drain bias voltages, e.g. above 15 volts. Such degradation is significantly reduced by forming the drain (6) as a highly-doped semiconductor electrode layer (56) on part of an intermediate lower-doped layer (55) on the semiconductor film (2) forming the TFT channel. The drain electrode layer (56) is laterally separated from the transistor channel. An area (A) of the intermediate layer (55) not overlapped by the electrode layer (56) nor modulated by the gate (4) extends from the drain electrode layer (56) towards the gate (4) so as to provide along the intermediate layer (55) a low-doped field-relief region in at least part of the area of lateral separation. The TFTs may be, for example, of the coplanar type or even of the inverted staggered type.

Abstract: A semiconductor device (1) includes a vertical insulated gate field effect device (2) and has a semiconductor body (3) with a first semiconductor region (4) of one conductivity type adjacent one major surface (5). A second semiconductor region (6) of the opposite conductivity type is former within the first region (4) adjacent the surface (5) and a third region (7) forms with the second region (6) a rectifying junction (8) meeting the one major surface (5). A recess (9) extends into the first region (4) from the one major surface (5) so that the second and third regions (6 and 7) abut the recess (9), and an insulated gate (10) is formed within the recess (9) for controlling conduction between the first and third regions (4 and 7) along a conduction channel area (61) of the second region (6).

Abstract: A method of manufacturing a semiconductor device comprising a buried channel field effect transistor, which method comprises the formation of a stack of layers on a substrate (1) with an active semiconductor layer (13, 14) having a non-zero aluminium (Al) content, a semiconductor cap layer (4) without aluminium (Al), a masking layer (100) provided with a gate opening (51); a first selective etching step by means of a fluorine (F) compound in the cap layer (4) down to the upper surface (22) of the active layer (13, 14) on which a stopper layer (3) of aluminum fluoride (AlF.sub.

Abstract: The invention relates to a charge coupled device with a buried channel in which charge is detected by a MOST (MOS transistor) incorporated in the channel and having a surface channel of the conductivity type opposed to that of the charge coupled device. The source zone is situated in the centre of the CCD channel and is formed simultaneously with the channel bounding zone. The gate electrode comprises two portions situated on either side of the source zone, which portions, seen at the surface, do not overlap the source and drain zones. Below the gate electrode, a zone is formed of the same conductivity type as but with a higher doping than the CCD channel, which zone forms a charge storage region for the charge packet to be read out during the reading-out process. The source and drain zones are connected to the MOST channel region by means of extensions. The detector can be manufactured in a self-aligned manner, has a high charge storage capacity, a good noise behaviour, and a high speed.

Abstract: A power semiconductor device (4) has a main current carrying section (4a) with a number of parallel-connected active device cells (5) and a first main electrode (6) coupled to a first terminal (2), a second main electrode (7) connected to a second terminal (3) and a control electrode (8) and a sense current carrying section (4b) with at least one sense cell (5a) similar to the active device cells (5) and having a first main electrode (6) coupled to the first terminals (2) and a second main electrode (9). A current sensing arrangement (10) has a first resistor (R1) coupling the second main electrode (9) of the sense current carrying section (4b) to the second terminal (3), a second resistor (R2) similar to the first resistor (R1) and a current source (11) coupled in series with the second resistor to the second terminal (3) for supplying a reference current (Ir) through the second resistor (R2).

Abstract: A power semiconductor device (P) has first and second main electrodes (D) and (S) for coupling a load (L) between first and second voltage supply lines (2 and 3), a control electrode (G) coupled to a control voltage supply line (4) and a sense electrode (S1) for providing in operation of the power semiconductor device (P) a current that flows between the first and sense electrodes (D and S1) and is indicative of the current that flows between the first and second main electrodes (D and S). A current mirror arrangement (5) is provided having a first current path (5a) for passing a given current (I.sub.1) and a second current path (5b) for mirroring the given current. A control semiconductor device (M3) has first and second main electrodes (d and s) coupled between the control electrode (G) and the second main electrode (S) of the power semiconductor device (P) and a control electrode (g) coupled to the second current path (5b).

Abstract: A lateral thin-film silicon-on-insulator (SOI) device includes a lateral semiconductor device such as a diode or MOSFET provided in a thin semiconductor film on a thin buried oxide. The lateral semiconductor device structure includes at least two semiconductor regions separated by a lateral drift region. By providing a substantially linear lateral doping profile in the lateral drift region, and by providing a conductive field plate on a linearly-graded top oxide insulating layer, a device structure is obtained in which conduction losses can be reduced without reducing breakdown voltage.

Abstract: The invention relates to a method of manufacturing a flexible fastening member (19) comprising a foil (1) for fastening an object (15) thereto, characterized by making at least two generally U-shaped incisions (5) which are spaced apart, which define a central portion (23) between them, and which are directed oppositely to another, the open ends of the U-shapes facing away from another so as to create two mutually opposed tags (11), and by bending the foil (1) along two parallel bending lines (13), each line being situated at the open end of a U-shaped incision (5) so as to obtain a generally U-shaped member (19) whose base is said central portion (23), and to obtain the tags (11) as extensions of the legs (25) of said U-shaped member and situated at one side of the plane (20) defined by the central portion (23), the legs (25) being situated at the other side of said plane (20).

Abstract: Digital transmission system (10) for digitally modulated signals, comprising a receiving device (14) which includes a demodulator (110), processing apparatus (120) and carrier synchronizing apparatus (16) for estimating and compensating for synchronization errors. The synchronizing apparatus includes a first loop (1) for phase/frequency correction and a second loop (2) for phase correction, the operation of these loops being controlled by a mode detector (130) depending on whether the receiving device is seeking to unlock or lock. The second loop (2) transforms a phase error signal into a phase correction signal which is mixed in mixer (246) with the signal coming from the demodulator. Preferably, the signals are modulated via a coded modulation.

Abstract: The application describes a network comprising transceivers (1..6) linked in a network topology. The positions of the transceivers in the network topology are changed in dependence on the loads on the end-to-end connections (VC1..VC5) between the transceivers in the network. A configuration is chosen to give efficient use of the capacity available in the network. Each time that a new end-to-end connection (VC) within the network is set up the positions of the transceivers (1..6) are changed such that the network remains optimized.