Abstract: In the manufacture of integrated circuits, damage to transistors caused by ESD is customarily precluded by connecting the gates of the transistors, in an early stage, to a protection diode. If, for example during plasma etching or reactive ion etching, an electric charge is stored on a floating gate, this charge can be removed via the diode before electric breakdown occurs. In a first embodiment of a device in accordance with the invention, the diode is formed in an active region covered by an electrically insulating layer 12. The gate 8, or a poly track 9 connected thereto, projects above this layer and covers only a part of the active region. In the uncovered part of the active region, a cathode or anode is provided so as to be self-aligned relative to the poly track. In another embodiment, the poly track 9 is situated directly next to the region of the diode. The poly track 9 and the surface zone 10 of the protection diode are interconnected by an overlapping metal contact 15.

Abstract: A communication system with a control circuit is disclosed. The circuit includes an operating system for exchanging messages and user software, and a device for exchanging software. For a software component to be exchanged in a few milliseconds, a newly loaded software component, corresponding to a successor component, obtains states and messages from a service port of a stopped software component that is to be replaced, corresponding to a predecessor component. The successor component is restarted with the transferred states and messages.

Abstract: A conversion device includes an A/D converter (8) and a control module for auto-adjustment of the DC component. This module includes an analog comparator (5) which performs a comparison between the analog signal (11) at the input of the A/D converter (8) and a reference voltage (10) produced on the basis of voltages which feed the resistance ladder (9) of the converter. In order that the control does not introduce noise into the signal supplied, the comparator (5) of the control module has a non-linear response with a reduced output/input gain for a range of the differential control signal centered around zero.

Abstract: A video graphics controller (VGC) for communicating with a frame buffer memory and a display device includes a first-in, first-out (FIFO)-configured memory, a memory controller for communicating with the frame buffer memory and controlling the FIFO-configured memory, and read and write pointers for the FIFO-configured memory. A subtractor is coupled to the read and write pointers for generating a difference signal which is coupled to the memory controller, and the read pointer generates a read carrier signal which is provided to a lock detector along with an end-of-frame signal. The lock detector generates an output signal which is coupled to the memory controller in order to place the video graphics controller in a locked mode of operation if no read carry signal is generated during an inputting of an entire frame of information into the FIFO-configured memory, and in an unlocked mode of operation if a read carry signal is generated prior to the completion of the inputting of an entire frame of information.

Abstract: A circuit arrangement includes a first differential amplifier stage with two amplifier members whose main current paths are coupled to one another and, via a first reference current source, to a first reference potential, and are coupled to a respective output terminal as well as, via a respective output impedance, to a second reference potential, and whose control terminals can be supplied with a first control signal, an output signal being available at the output terminals. At least one further differential amplifier stage is provided, each of which includes two further amplifier members whose main current paths are coupled to one another and, via a respective further reference current source, to the first reference potential and whose control terminals can be supplied with (a) further control signal(s).

Abstract: A method of biasing an MOS IC includes the steps of providing the IC with two MOS transistors having substantially similar characteristics and maintaining these two transistors at different temperatures. During operation of the IC, an output voltage is generated from each of the two transistors, and a bias voltage is generated as a function of the difference between the two output voltages. This bias voltage is then fed back to the gate terminals of the two MOS transistors to set the bias voltage to a steady-state level at which the circuit will operate at a zero temperature coefficient point. This bias voltage is also coupled to the gate electrodes of other transistors within the IC, to operate these transistors at the zero temperature coefficient point. An IC operated in accordance with biasing method will exhibit superior stability with variations in ambient temperature.

Abstract: A lateral thin-film Silicon-On-Insulator (SOI) JFET device includes a semiconductor substrate, a buried insulating on the substrate, and a JFET device in a thin semiconductor layer of a first conductivity type on the buried insulating layer. The device includes a source region of the first conductivity type, a control region of a second conductivity type which is laterally spaced apart from the source region and a lateral drift region of the first conductivity type adjacent to the control region. A drain region of the first conductivity type is provided laterally spaced apart from the control region in a first lateral direction by the lateral drift region, and at least one field plate electrode is provided over at least a major portion of the lateral drift region and is insulated from the drift region by an insulation region.

Abstract: The array comprises an insulating substrate with diode-capacitor pixels disposed over conductors on the substrate. A single mask is used to etch the pixel stacks, and each pixel stack is wider than the conductor beneath. As a result, the mask alignment does not influence the pixel characteristics.

Abstract: A semiconductor memory device includes first and second conductive contact layers (12, 15) and an hydrogenated, silicon-rich, amorphous silicon alloy layer (14), particularly an amorphous silicon nitride or amorphous silicon carbide alloy, extending between the contact layers. A defect band is induced in the amorphous silicon layer which lowers the activation energy level for the transport of carriers through the structure by an amount that is selectable and determined by the defect band. The defect band is created by a programming process, for example, using current stressing or particle bombardment. A memory matrix array device is provided by forming a row and column array of such memory devices from common deposited layers on a common substrate with crossing sets of row and column conductors separated by a layer of the alloy material defining a memory device at each of their cross-over regions.

Abstract: A line driver comprising a first transistor (M1), a first amplifier (A1) and a reference resistor (10) for converting an input voltage (Vin) to a first current (i1) through the first transistor (M1). A second current i2=n*i1 flows through a second transistor (M2) which forms a 1:n current mirror with the first transistor (M1). The current i2 flows to a load (6), if so required via a transmission line (TL). The impedance of the load (6) is equal to the characteristic impedance RL of the transmission line (TL). Thus the impedance seen by the line driver is equal to RL. A second transconductance amplifier (A2) counteracts reflected signals in the output signal (Vout) caused by mismatch between the output impedance of the current mirror (M1, M2) and the impedance seen by the line driver.

Abstract: A method of manufacturing a semiconductor device with a bipolar transistor (1) and a MOS transistor (2) formed in a silicon body (3) which for this purpose is provided with a field insulation region (4) by which semiconductor regions (6, 7) adjoining a surface (5) of said body are mutually insulated. A first region (6) is destined for the bipolar transistor and a second region (7) for the MOS transistor. The second region is provided with a gate dielectric (10). Then an electrode layer of non-crystalline silicon (11) is provided on the surface, which electrode layer is provided with a doping and in which electrode layer subsequently an emitter electrode (12) is formed on the first region and a gate electrode (13) on the second region.

Abstract: A lateral thin-film Silicon-On-Insulator (SOI) device includes a lateral semiconductor device such as a diode or MOSFET provided in a thin semiconductor film on a thin buried oxide. The lateral semiconductor device structure includes at least two semiconductor regions separated by a lateral drift region. A top oxide insulating layer is provided over the thin semiconductor film and a conductive field plate is provided on the top oxide insulating layer. In order to provide enhanced device performance, a portion of the top oxide layer increases in thickness in a substantially continuous manner, while a portion of the lateral drift region beneath the top oxide layer decreases in thickness in a substantially continuous manner, both over a distance which is at least about a factor of five greater than the maximum thickness of the thin semiconductor film.

Abstract: A circuit that is easily configured to convert from a progressive scan image, e.g., at a resolution of 1280.times.720, to an interlaced image scan, e.g., at an interlaced resolution of 1920.times.1080 (1920.times.540 per field), or visa-versa. One arrangement of the circuit employs multiplexers so that the two conversion modes share the available hardware. The circuit is only marginally more complex than a circuit that can only do the conversion in one direction. The quality of the progressive-to-interlace conversion is acceptable for high-end interlaced display systems and the quality of the interlace-to-progressive conversion is at least high enough for "mid-range" progressive display systems.

Abstract: A circuit arrangement having at least two signal paths which can be alternately enabled by feeding respective controllable current sources and by logic signals selecting one of these controllable current sources, while, at a transition from one signal path to the other, the controllable current sources of the relevant two signal paths are controllable by a time-continuously changing control signal during a transition interval, such that currents which can be supplied by these two controllable current sources change continuously and in opposite directions.

Abstract: The illumination system (1) has a substrate (2) and an active layer (3) comprising an electroluminescent material, in which the active layer (3) is present between a first, optically transparent electrode layer (5) and a second electrode layer (7). The illumination system (1) is characterized in that a light-scattering layer (28) comprising a medium having light-scattering properties is present in a forward direction (29) with respect to the active layer (3), in which the non-scattered fraction of a (collimated) light beam, when passed through the light-scattering layer (8) in the forward direction (29), is in the range between 0.05 and 0.8, preferably in the range between 0.1 and 0.5. The light-scattering properties of the medium are preferably stronger as the light is more obliquely incident, as is achieved by using birefringent particles and/or media. A very suitable light-scattering layer (28) is a (half) monolayer of TiO.sub.

Abstract: Control circuit for generating two control currents for a variable gain amplifier having a gain which is substantially proportional to the ratio of the two control currents. For a gain control which is independent of the signal level of the variable gain amplifier an exponential control characteristic is needed. The control circuit generates a set of control currents 2*I and 2*J with a ratio which is pseudo-exponential dependent on the control parameter u.sub.c. The ideal exponential characteristic is approximated to with a second-order function of the type ((1+x)/(1-x)).sup.2 by means of a voltage-to-current converter, a first translinear loop and a second translinear loop.

Abstract: A service switching point having a direct memory access controller is used for controlling a data transfer between a data memory and an input/output device. There is proposed to provide the direct memory access controller for generating a first part of an address, and a generator for cyclically generating a second part of the address. Such a service switching point can preferably be used in PCM 30 transmission networks when a subscriber device is coupled to the service switching point via a DSV2 connecting line while 2.048 Mbit/s data rates occur.

Abstract: A capacitive sensing array device, such as a fingerprint sensing device, includes an array of individual sensing electrodes (14) covered by a layer of insulating material (40) defining a sensing surface on which a person's finger is placed, each sensing electrode, its overlying fingerprint portion and intervening insulating layer providing a capacitance in operation. The sensing electrodes are of chromium and the covering insulating material includes a thin layer of chromium oxide which offers excellent scratch resistance and can be formed conveniently by oxidation of a surface region of the sensing electrodes. In a row and column array, address lines (18) extending between rows of electrodes (14) may also include chromium and be covered by chromium oxide. Preferably, the sensing electrodes and address lines are defined from a common deposited chromium layer.

Abstract: A communication system comprises a communications network coupled at least to a terminal unit. The communications network is coupled to a service device which comprises a switching center, a controller, and a data bank. The data bank contains at least a service logical program. A terminal unit generates a first parameter and a second parameter for sending as a single transmission to the service device. The controller extracts a service logical program from the data bank in response to the first parameter. The controller further controls the switching center in response to the second parameter based on the extracted service logical program.

Abstract: A charge measurement circuit 20 includes a charge sensitive amplifier 40 which holds the input 42 at a constant voltage. A compensation circuit 72, 74, 76, 80 enables a current to be supplied to or drained from a charge supplying circuit 32. This current is selected such that any voltage mismatch between the output of the supplying circuit 32 and the input 42 of the measurement circuit 20 does not result in a charge flow which causes errors in the measured signal.