Abstract: A method of packaging an integrated circuit, including providing a lead frame having lead fingers, where the lead frame has a gold layer thereon on a top surface and a bottom surface. An integrated circuit die is attached to the lead frame. The gold layer is substantially removed from portions of the top surface of the lead frame. The integrated circuit die is wire bonded to the lead fingers with a plurality of wire stitches subsequent to substantially removing the gold. The die is encapsulated in a mold compound to form a packaged integrated circuit.

Abstract: A semiconductor device assembly can include a semiconductor chip, a receiving substrate, and a spacer structure interposed between the semiconductor chip and the receiving substrate. The spacer provides an unoccupied space between a pillar and a bond finger for excess conductive material, which can otherwise flow from between the pillar and bond finger and result in a conductive short. The spacer can also provide an offset between the pillar and bond finger.

Abstract: A method and apparatus for assembling a semiconductor device. A chip (901) with solder bodies (903) on its contact pads is flipped onto a substrate (904). After the reflow process, a gap (910) spaces chip and substrate apart. A polymer precursor is selected for its viscosity of known temperature dependence. The apparatus has a plate (800) with heating and cooling means to select and control a temperature profile from location to location across the plate. After preheating, the assembly is placed on a mesa (801) of the plate configured to heat only a portion of the substrate. Movable capillaries (840, 921) blow cooled gas onto selected locations of the assembly. After the temperature profile is reached, a quantity of the precursor is deposited at a chip side and pulled into the gap by capillary action. The capillary flow is controlled by controlling the precursor viscosity based on the temperature profile, resulting in a substantially linear front, until the gap is filled substantially without voids.

Abstract: A semiconductor chip 101 with surface 101b free of circuitry assembled on a metal carrier 102 by an attachment layer 103 with thickness 103a. Included in layer 103 are metal bodies 104 and an adhesive polymeric compound 105 between bodies 104. Metal bodies 104 form metal inter-diffusions with carrier 102 and extend from the carrier across thickness 103a, stopping at and contacting second chip surface 101b. The high thermal conductivity of metal bodies 104 greatly increases the thermal conductivity of the attachment layer. The metal bodies may be arrayed in a regularly spaced pattern in x- and y-directions, as well as in enhanced concentrations in locations of thermal hot spots and of high thermomechnical stresses. In the latter application, the metal bodies prevent the growth of microcracks and delamination.

Abstract: An integrated circuit (IC) includes self-calibrating programmable digital logic circuitry. The IC includes at least one programmable digital logic cell, wherein the first programmable digital logic cell provides (i) a plurality of different accessible circuit configurations or (ii) a voltage level controller. A self-calibration system is provided that includes at least one reference device, a measurement device for measuring at least one electrical performance parameter that can affect a processing speed of the first programmable digital logic cell or at least one parameter that can affect the electrical performance parameter using the reference device to obtain calibration data. A processing device maps the calibration data or a parameter derived therefrom to generate a control signal that is operable to select from the plurality of different accessible circuit configurations or a voltage level output to change the processing speed of the programmable digital logic cell.

Abstract: An integrated circuit (IC) includes a substrate having a top side having active circuitry thereon including a plurality of metal interconnect levels including a first metal interconnect level and a top metal interconnect level, and a bottom side. At least one TSV array includes a plurality of TSVs. The TSVs are positioned in rows including a plurality of interior rows and a pair of exterior rows and a plurality of columns including a plurality of interior columns and a pair of exterior columns. At least a portion of the TSVs in the array are electrically connected TSVs that are coupled to a TSV terminating metal interconnect level selected from the plurality of metal interconnect levels. At least one of the exterior rows or exterior columns include a lower number of electrically connected TSVs compared to a maximum number of electrically connected TSVs in the interior rows and interior columns, respectively.

Abstract: A Viterbi decoder includes a branch metric unit, an add-compare select unit coupled to the branch metric unit, and a trace-back unit coupled to the add-compare select unit. The branch metric unit includes a branch metric computation unit coupled to a thresholder unit. The branch metric computation unit is configured to compute a branch metric. The thresholder unit is configured to compare the branch metric with a threshold value. If the branch metric is greater than the threshold value, the thresholder unit is configured to forward the threshold value to the add-compare select and not forward the branch metric to the add-compare select unit. Implementing such a branch metric ceiling allows for a predictable reduction in the significant bits of calculations in the Viterbi decoder, which allows for reduction of complexity via elimination of gates and storage elements.

Abstract: Embodiments provide systems and methods to optimize the time when to transmit a silencing frame, and hence, improve the overall network throughput and avoid access point transmission rate fall-back mechanism having an avalanche effect during coexistence of dissimilar wireless network technologies. A receiver comprises at least two dissimilar network technology subsystems, at least one subsystem of which is higher priority than at least another of the dissimilar subsystems. In some embodiments, a receiver is able to transmit a silencing frame during a predetermined transmission window within a lower priority technology network interval. In other embodiments, a receiver calculates a predetermined transmission window, the predetermined transmission window to occur within a lower priority technology network interval, and transmits a silencing frame during the predetermined transmission window.

Abstract: Embodiments provide novel systems and methods for multiple-input multiple-output (MIMO) Max-Log detection. These systems and methods enable near-optimal performance with low complexity for a two-input two-output channel. Some embodiments comprise using a Max-Log detector to compute a set of log-likelihood ratio (LLR) values for a channel input by minimizing cost function while computing only one instance of the cost function for each value of each bit in a symbol. Other embodiments comprise using a Max-Log detector to compute a set of log-likelihood ratio (LLR) values for a channel input by computing all instances of a cost function for each value of each bit in a symbol and selecting the minimum cost from all computed instances of the cost function for each value of each bit.

Abstract: A network element including a processor with logic for managing packet queues by way of packet descriptor index values that are mapped to addresses in the memory space of the packet descriptors. A linking memory is implemented in the same integrated circuit as the processor, and has entries corresponding to the descriptor index values. Each entry can store the next descriptor index in a packet queue, to form a linked list of packet descriptors. Queue manager logic receives push and pop requests from host applications, and updates the linking memory to maintain the queue. The queue manager logic also maintains a queue control register for each queue, including head and tail descriptor index values.

Abstract: A receiver system for receiving and decoding modulated communications signals in a multiple-input, multiple-output (MIMO) environment, where the signals are modulated according to Orthogonal Frequency Division Modulation (OFDM). The receiver system includes shared decoder logic circuitry that executes a maximum-likelihood (ML) estimation algorithm in deriving the signals transmitted from the multiple transmitting antennae, as those signals were received over all of the receiving antennae. For a control channel portion of the data frame, the shared decoder logic circuitry applies Viterbi decoding to the transmitted datastreams estimated by the ML estimation algorithm. This sharing of decoder logic reduces the integrated circuit chip area, and also power dissipation, otherwise required in performing these complex decoding functions.

Abstract: A method and system for estimating noise variance. A method for noise variance estimation comprises receiving a first multi-sample symbol and receiving a second multi-sample symbol. The first multi-sample symbol is subtracted from the second multi-sample symbol to produce a set of noise samples. The set of noise samples is used to produce a noise variance estimate. The noise variance estimate is applied in various tasks (e.g. channel estimation, log-likelihood ratio computation, and/or minimum mean squared error equalization) to process data provided to a user.

Abstract: A switch mode power converter that precisely controls average switching current and operating frequency. The switching control operative in hysteretic average current mode control provides wide bandwidth operation without the need for slope correction. The switching converter ripple current is varied by a frequency comparator in response to a comparison of the switching frequency to a reference frequency. The ripple current is adjusted to obtain correlation between the operating switching frequency and the reference frequency. Peak current levels are precisely controlled and may be limited to prevent component stress levels from being exceeded. Current levels are continuously monitored with a current sense amplifier, or monitored with a high-gain low energy current sampler. Feedback loop independent line and load regulation is provided by continuous current monitoring, or by using variable slope charge and transfer voltage to pulse width converters when operating with a current sampler based system.

Abstract: A system and method for sidelobe suppression in OFDM communications systems is provided. A method for transmitting an information symbol having a plurality of information sub-carriers and a plurality of active interference cancellation (AIC) sub-carriers includes generating AIC sub-carrier data based on the information to be transmitted, populating the plurality of information sub-carriers with the information, populating the plurality of AIC sub-carriers with the AIC sub-carrier data, applying baseband processing to the information symbol, thereby producing a processed symbol, and transmitting the processed symbol.

Abstract: Systems and methods for dual-carrier modulation (DCM) encoding and decoding for communication systems. Some embodiments comprise a DCM encoder for applying a pre-transmission function to at least one 16-QAM input symbol and mapping resulting transformed symbols onto at least one larger constellation prior to transmission. Some embodiments joint decode, by a DCM decoder, a predetermined number of received data elements and compute a set of log-likelihood ratio (LLR) values for at least eight bits from a resulting at least one transformed symbol.

Abstract: A method and apparatus for detecting symbols in a Multiple-Input Multiple-Output Orthogonal Frequency Division Multiplexing (“MIMO-OFDM”) system. A MIMO-OFDM receiver includes a first detector that estimates a symbol of a first MIMO-OFDM sub-carrier and a second detector that estimates a symbol of a second MIMO-OFDM sub-carrier. The second detector differs in complexity from the first detector. A detector control block is coupled to the detectors. The detector control block assigns the first detector to process the first MIMO-OFDM sub-carrier and assigns the second detector to process the second MIMO-OFDM sub-carrier. The detector control block computes a list metric for a sub-carrier. Based on the list metric the detector control block assigns a candidate symbol list length to the detector processing the sub-carrier. Alternately, the detector control block assigns one of a variety of detector types to a sub-carrier based on the sub-carrier list metric.

Abstract: A system comprises a wireless device that communicates across a spectrum having a plurality of sub-channels. The wireless device comprises a plurality of antennas through which the wireless device communicates with another wireless device, wherein each antenna communicates with the other wireless device via an associated communication pathway. The wireless device further comprises sub-channel power analysis logic coupled to the antennas and adapted to determine which communication pathway has the highest communication quality on a sub-channel by sub-channel basis. The wireless device still further comprises diversity selection logic coupled to the sub-channel power analysis logic and adapted to determine a weighting vector for an associated antenna based on the communication quality, wherein the weighting vector specifies a relative transmission power for each sub-channel for the associated antenna.

Abstract: Embodiments provide a system and method for efficiently classifying different channel types in an orthogonal frequency division multiplexing (OFDM) system. Embodiments quantify the frequency selectivity in a channel by measuring the variation in a particular channel statistic across sub-carriers in an OFDM system, involve minimal complexity in implementation, and can be used in a variety of scenarios. One embodiment is a method for classifying channels in an OFDM system, comprising measuring variation of at least one channel statistic across sub-carriers, quantifying the variation to determine a measurement value, and applying the measurement value to at least one threshold to classify the channel.

Abstract: An ultrasound device generates polar-coordinate image data divided up into an (N×M) array of polar-coordinate image data blocks; a first external memory configured to store the (N×M) array of data blocks; a second external memory configured to store x-y coordinate image data corresponding to the polar-coordinate image data; a video processing chip comprising an internal memory configured to store an (N×R) array of the polar-coordinate image data blocks; and a controller configured to perform a data conversion operation on the (N×R) array of data blocks to generate x-y coordinate image data, and to store the x-y coordinate image data to the second external memory. N, M, and R are integers greater than 1; R is less than M; and an internal access time for the internal memory element is shorter than an external access time for the first external memory element.

Abstract: A system comprising communication logic capable of receiving data signals from a network. The signals comprise both erasure error and random error. The system also comprises processing logic coupled to the communication logic and adapted to partition parity check bytes of the received signals into a first portion and a second portion. The processing logic uses the first portion for random error correction and the second portion for erasure error correction.