Patents Represented by Attorney, Agent or Law Firm Steven Shaw
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Patent number: 8154109Abstract: A lead frame (410) including a die pad (100) for mounting at least one integrated circuit (405) thereon and a plurality of lead fingers (413). The die pad (100) includes a metal including substrate (105) having a periphery that includes a plurality of sides (111-114), an intersection of the sides forming corners (115). A first plurality of grooves including least one groove (106) is formed in a top side surface of the substrate and is associated with each of the corners (115). The groove (106) has a dimension oriented at least in part at an angle of 75 to 105 degrees relative to a bisecting line (118) originating from the corners (115). A lead-frame-based packaged semiconductor device (400) includes a lead frame (410) including at least one metal comprising die pad (418) and a plurality of lead fingers (413) around the die pad (418). At least one integrated circuit (405) is mounted on the top surface of the die pad (418), and electrically connected to the plurality of lead fingers (413).Type: GrantFiled: September 23, 2010Date of Patent: April 10, 2012Assignee: Texas Instruments IncorporatedInventors: Kapil H Sahasrabudhe, Steven A Kummerl
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Patent number: 8154117Abstract: An integrated circuit (IC) includes a substrate having a semiconducting surface, a first array of devices on and in the semiconducting surface including first and second coacting current conducting nodes, a plurality of layers disposed on the substrate and including at a electrically conductive layers and dielectric layer, and a plurality of bump pads on or in the top surface of the dielectric layers. In the IC, the electrically conductive layers define electrical traces, where a first portion of the electrical traces contact a first portion of the bump pads exclusively to a portion of the first coacting current conducting nodes, where a second portion of the electrical traces contact a second portion of the bump pads exclusively to a portion of the second coacting current conducting nodes, and where the electrical traces are electrically isolated from one another by the dielectric layers.Type: GrantFiled: December 31, 2008Date of Patent: April 10, 2012Assignee: Texas Instruments IncorporatedInventors: Stefan W. Wiktor, Vladimir A. Muratov, Anthony L. Coyle, Bernhard P. Lange
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Methods and apparatus to prevent mold compound feeder jams in systems to package integrated circuits
Patent number: 8151995Abstract: Methods and apparatus to preventing mold feeder jams in a system to package integrated circuits. An example method includes detecting if a mold compound tablet has a first alignment on a path and removing the mold compound tablet from the path if the mold compound tablet has a second alignment different from the first alignment.Type: GrantFiled: February 4, 2008Date of Patent: April 10, 2012Assignee: Texas Instruments IncorporatedInventors: Chih-Chung Chen, Chih-Hsien Lin, Tsung-Chi Chiang -
Patent number: 8154443Abstract: A system and method for operating a wireless transmitter and a global navigation satellite (“GNSS”) receiver coexistent in a mobile wireless device. A mobile wireless device includes a GNSS receiver and a wireless networking system. The wireless networking system includes a wireless transmitter. The wireless transmitter provides a first interference level signal to the GNSS receiver. The first interference level signal indicates a level of interference that the GNSS receiver can expect due to operation of the transmitter.Type: GrantFiled: February 27, 2009Date of Patent: April 10, 2012Assignee: Texas Instruments IncorporatedInventors: Ariton E. Xhafa, Deric W. Waters
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Patent number: 8155600Abstract: Systems and methods for digital communication using an inexpensive reference crystal are described herein. Some illustrative embodiments include a method that includes setting a center frequency of a local oscillator used by a radio frequency (RF) transceiver, sequentially applying each of a plurality of predetermined offsets to the center frequency of the local oscillator, determining a plurality of metrics indicative of the quality of a received signal (each of the plurality of metrics corresponding to a different predetermined offset of the plurality of predetermined offsets), and selecting a predetermined offset of the plurality of predetermined offsets that results in a metric indicating a received signal that is higher in quality than the received signal that results when applying each of the remaining predetermined offsets of the plurality of offsets.Type: GrantFiled: December 3, 2007Date of Patent: April 10, 2012Assignee: Texas Instruments IncorporatedInventors: Yehuda Azenkot, Manoneet Singh
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Patent number: 8154134Abstract: A packaged electronic device includes a leadframe including a die pad, a first, second, and third lead pin surrounding the die pad. An IC die is assembled in a face-up configuration on the lead frame. The IC die includes a substrate having an active top surface and a bottom surface, wherein the top surface includes integrated circuitry including an input pad, an output pad, a power supply pad, and a ground pad, and a plurality of through-substrate vias (TSVs) including an electrically conductive filler material and a dielectric liner. The TSVs couple the input pad to the first lead pin, the output pad to the second lead pin, the power supply pad to a third lead pin or a portion of the die pad. A fourth TSV couples pads coupled to the ground node to the die pad or a portion of the die pad for a split die pad.Type: GrantFiled: May 8, 2009Date of Patent: April 10, 2012Assignee: Texas Instruments IncorporatedInventors: Thomas D. Bonifield, Gary P. Morrison, Rajiv Dunne, Satyendra S. Chauhan, Masood Murtuza
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Patent number: 8156334Abstract: Methods for key exchange and mutual authentication are provided that allow for inherent authentication and secret key derivation of parties communicating through an unsecured medium. These methods allow for greater security than existing key exchange and authentication methods while requiring little or no additional energy or time compared with a basic Diffie-Hellman key exchange. These methods allow for secure communication with small, low-power devices and greater security for any devices communicating through an unsecured medium.Type: GrantFiled: August 12, 2009Date of Patent: April 10, 2012Assignee: Texas Instruments IncorporatedInventor: Jin-Meng Ho
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Patent number: 8144807Abstract: A digital subscriber line (DSL) modem that has a canceller digital filter for cancelling crosstalk and RF interference in a received DSL signal is disclosed. The modem includes common-mode sense circuitry and also differential-mode sense circuitry. Samples of the common-mode signal are acquired during a “quiet” period of initialization of the DSL modem, and samples of the differential-mode signal are acquired during live transmission of a DSL signal. An estimate of an autocorrelation function is obtained from the common-mode samples, and a cross-correlation of the common-mode samples and differential-mode samples is also estimated. Digital filter coefficients are derived from these estimates, based on the assumption that the common-mode samples acquired during the “quiet” phase represent crosstalk and RF interference present during differential-mode communications.Type: GrantFiled: July 30, 2007Date of Patent: March 27, 2012Assignee: Texas Instruments IncorporatedInventors: Khashayar Mirfakhraei, Youngjae Kim
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Patent number: 8143704Abstract: An electronic assembly includes an IC die including a semiconductor top surface having active circuitry thereon and a bottom surface, and at least one protruding bonding feature having sidewall surfaces and a leading edge surface extending outward from the IC die. A workpiece has a workpiece surface including at least one electrical connector and at least one framed hollow receptacle coupled to the electrical connector. The receptacle is formed from metal and includes sidewall portions and a bent top that defines a cavity. The bent top includes bent peripheral shelf regions that point downward into the cavity and towards the sidewall portions. The protruding bonding feature is inserted within the cavity of the receptacle and contacts the bent peripheral shelf regions along a contact area to form a metallic joint, wherein the contact area is at least primarily along the sidewall surfaces.Type: GrantFiled: October 2, 2009Date of Patent: March 27, 2012Assignee: Texas Instruments IncorporatedInventor: Jeffrey A West
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Patent number: 8138026Abstract: A leadframe with a structure made of a base metal (105), wherein the structure has a plurality of surfaces. On each of these surfaces are metal layers in a stack adherent to the base metal. The stack comprises a nickel layer (201) in contact with the base metal, a palladium layer (202) in contact with the nickel layer, and an outermost tin layer (203) in contact with the palladium layer. In terms of preferred layer thicknesses, the nickel layer is between about 0.5 and 2.0 ?m thick, the palladium layer between about 5 and 150 nm thick, and the tin layer less than about 5 nm thick, preferably about 3 nm. At this thinness, the tin has no capability of forming whiskers, but offers superb adhesion to polymeric encapsulation materials, improved characteristics for reliable stitch bonding as well as affinity to reflow metals (solders).Type: GrantFiled: December 10, 2010Date of Patent: March 20, 2012Assignee: Texas Instruments IncorporatedInventor: Donald C Abbott
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Patent number: 8135563Abstract: An apparatus for evaluating a system. The apparatus can include a storage element for receiving at least one time-varying output characteristic of the system, the time-varying output characteristic comprising a plurality of raw data points representing a plurality of measurements at a plurality of times; and a processing element communicatively coupled to the storage element. The processing element can be configured for partitioning the plurality of raw data points into a plurality of segments, calculating a plurality of estimated data points based on a plurality of mathematical expressions, and characterizing the system based on at least one figure of merit (FOM) computed from the plurality of estimated data points. In the apparatus, at least one of the plurality of mathematical expressions is associated with each of the plurality of segments.Type: GrantFiled: September 30, 2008Date of Patent: March 13, 2012Assignee: Texas Instruments IncorporatedInventors: Ganesh Parasuram Srinivasan, Friedrich Johannes Taenzler
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Patent number: 8133763Abstract: A method for fabricating a leadframe for a QFN/SON semiconductor device by selecting (301) a strip of a first metal as the leadframe core, then plating (302) a layer of a second metal over both surfaces of the strip, then cutting (304) a pattern from the pre-plated strip and further removing (304) portions of the second metal layer over a surface to expose the underlying core first metal. The exposed core first metal oxidized (305) before using (306) the leadframe for assembling the semiconductor device. The steps of cutting and removing are performed programmable machining techniques such as computer numerical controlled tools (CNC), electrical discharge machining (EDM), laser cutting, and water jet cutting.Type: GrantFiled: August 28, 2009Date of Patent: March 13, 2012Assignee: Texas Instruments IncorporatedInventor: Sreenivasan K. Koduri
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Patent number: 8133761Abstract: A semiconductor system (200) of one or more semiconductor interposers (201) with a certain dimension (210), conductive vias (212) extending from the first to the second surface, with terminals and attached non-reflow metal studs (215) at the ends of the vias. A semiconducting interposer surface may include discrete electronic components or an integrated circuit. One or more semiconductor chips (202, 203) have a dimension (220, 230) narrower than the interposer dimension, and an active surface with terminals and non-reflow metal studs (224, 234). One chip is flip-attached to the first interposer surface, and another chip to the second interposer surface, so that the interposer dimension projects over the chip dimension. An insulating substrate (204) has terminals and reflow bodies (242) to connect to the studs of the projecting interposer.Type: GrantFiled: June 17, 2009Date of Patent: March 13, 2012Assignee: Texas Instruments IncorporatedInventors: Mark A Gerber, Kurt P Wachtler, Abram M. Castro
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Patent number: 8129224Abstract: A thermal management configuration for a flip chip semiconductor device is disclosed. The device includes a high power silicon based die having a metal bonding surface. A plurality of interconnects are formed on the metal surface and connected to a substrate. A plurality of thermal management stud bumps are formed on the metal bonding surface, the thermal management stud bumps positioned distinct from the interconnects and local to die hot spots, exposed ends of the thermal management stud bumps spaced from the substrate.Type: GrantFiled: October 18, 2010Date of Patent: March 6, 2012Assignee: Texas Instruments IncorporatedInventors: Siva P Gurrum, Kapil H Sahasrabudhe, Vikas Gupta
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Patent number: 8129227Abstract: A packaged surface-mount semiconductor device has the outer, un-encapsulated lead segments structured in five adjoining portions: The first portion protrudes from the encapsulation about horizontally; the second portion forms a convex bend downwardly; the third portion is approximately straight downwardly; the fourth portion forms a concave bend upwardly; and the fifth portion is straight horizontally. Each segment has across the width a first groove in the third portion, either on the bottom surface or on the top surface. Preferably, the groove is about 2 leadframe thicknesses vertically over the bottom surface of the fifth lead portion. When stamped, the groove may have an angular outline about 5 and 50 ?m deep; when etched, the groove may have an approximately semicircular outline about 50 to 125 ?m deep. A second groove may be located in the second segment portion; a third groove may be located in the transition region from the third to the fourth segment portions.Type: GrantFiled: September 20, 2010Date of Patent: March 6, 2012Assignee: Texas Instruments IncorporatedInventor: John P Tellkamp
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Patent number: 8130653Abstract: Network circuitry and a method of operating the same in establishing and deleting a service flow in a wireless network. A network station receives a request, from an initiating network station, to establish a service flow. The network station receiving the request issues a response to that request, following which it expects an acknowledgement from the initiator. Upon absence of such an acknowledgement, the receiving station transmits a message, to the initiator, to explicitly delete the service flow. This ensures that the initiator is not placed into an ambiguous state of transmitting payload traffic to a receiver that is ignoring or not receiving that traffic, in the case in which the initiator is also the transmitter of the payload traffic. This circuitry and method also ensures that the initiator is not in an ambiguous state, in the case in which it is the intended receiver of the payload traffic.Type: GrantFiled: March 19, 2008Date of Patent: March 6, 2012Assignee: Texas Instruments IncorporatedInventors: Harshal S. Chhaya, Ramanuja Vedantham
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Patent number: 8131230Abstract: A system and method for operating an FM system and wireless networking system coexistent in a mobile wireless device. A mobile wireless device includes a frequency modulation (“FM”) system that includes an FM transmitter and, optionally, an FM receiver. The mobile wireless device also includes a wireless networking system having a network receiver. The FM system is configured to disable the FM transmitter if an amplitude of a modulating signal provided to the FM transmitter is below a predetermined threshold.Type: GrantFiled: February 27, 2009Date of Patent: March 6, 2012Assignee: Texas Instruments IncorporatedInventors: Ariton E. Xhafa, Deric W. Waters
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Patent number: 8129228Abstract: An integrated circuit package that comprises a lead frame, an integrated circuit located on the lead frame and a shunt resistor coupled to the lead frame and to the integrated circuit. The shunt resistor has a lower temperature coefficient of resistance than the lead frame, and the lead frame has a lower resistivity than the shunt resistor. The shunt resistor has a low-resistance coupling to external leads of the lead frame, or, the shunt resistor has its own integrated external leads.Type: GrantFiled: October 25, 2010Date of Patent: March 6, 2012Assignee: Texas Instruments IncorporatedInventors: Ubol Udompanyavit, Sreenivasan K Koduri, Gerald W Steele, Jason M Cole, Steven Kummerl
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Patent number: 8130032Abstract: The invention relates to systems and methods for high-sensitivity detection of input bias current. The invention more particularly relates to platforms and techniques for the calibration and measurement of input bias current in op amps or other devices. In embodiments, the platform can incorporate a servo loop connected to a high-sensitivity test amplifier, such as an instrumentation amplifier. The test amplifier can complete a switchable circuit with the servo loop and detect a calibration input bias current for the test platform, without a production device in place. The device under test can be switched into the servo loop, and the total bias current measured with both the device under test and test amplifier in-circuit. The difference between the measured current with the device inserted and the previously measured calibration current represents the bias current for the subject device, without attaching external meters or requiring reference parts of the production type.Type: GrantFiled: September 29, 2010Date of Patent: March 6, 2012Assignee: Texas Instruments IncorporatedInventors: Dale Alan Heaton, David Walker Guidry
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Patent number: 8130791Abstract: A receiver which receives a stream of data packets including video data packets over a physical data link and drops data packets when an error on a physical communication layer is detected, wherein the receiver comprises a processor, configured so that it is able to check whether the received data packet is a video packet and whether it is corrupted by an error on the physical communication layer. If this is the case, the video packet is marked as corrupted and forwarded to the network layer. There is further provided a method for processing a stream of data packets including video data packets, the method including checking for each data packet whether it is a video data packet; checking for each video data packet whether it is corrupted by an error on the physical communication layer; marking a video packet as corrupted if it is corrupted due to an error on the physical communication layer; and forwarding the marked corrupted video packet to the network layer.Type: GrantFiled: June 13, 2008Date of Patent: March 6, 2012Assignee: Texas Instruments IncorporatedInventors: Thomas Leyrer, Krzysztof Chruscinski