Abstract: A method for forming electronic assemblies includes providing a plurality of IC die each having IC bonding conductors and a workpiece having workpiece bonding conductors. A curable dielectric film is applied to the IC bonding conductors or the workpiece surface. The plurality of IC die are placed on the workpiece surface so that the plurality of IC bonding conductors are aligned to and face the plurality of workpiece bonding conductors to provide a first bonding. The placing is performed at a vacuum level corresponding to a pressure <1 kPa, and at a temperature sufficient to provide tackiness to the curable dielectric film. The plurality of IC die are then pressed to provide a second bonding. A temperature during pressing cures the curable dielectric film to provide an underfill and forms metallic joints between the plurality of IC bonding conductors and the plurality of workpiece bonding conductors.

Abstract: The invention relates to leadframes and semiconductor chip package assemblies using leadframes, and to methods for their assembly. A disclosed embodiment of the invention includes a semiconductor package leadframe with a chip mounting surface for receiving a semiconductor chip and a plurality of leadfingers. The leadfingers have a proximal end for receiving one or more wirebond, and a distal end for providing an electrical path from the proximal end. One or more of the leadfingers also has an offset portion at its proximal end for increasing the clearance between the leadfinger and underlying heat spreader, increasing the stiffness of the leadfinger, and increasing leadfinger deflection-resistance and spring-back. The offset is in the direction opposite the plane of a heat spreader thermally coupled to the mounting surface.

Abstract: A network includes an access point and a station. The station transmits to the access point a current clear-to-send packet at a current time during a current exchange. The transmission is based on success or failure of a previous exchange during which a previous clear-to-send packet was transmitted at a previous time.

Abstract: An IC die includes active circuitry and I/O nodes tied together in first net and at least a second net. A first die pad and a second die pad adjacent thereto are coupled to the first and second net, respectively. A redirect layer (RDL) coupled to the die pads over a first dielectric vias includes a first RDL trace lateral coupling the first die pad and first RDL pad and a second RDL trace coupling the second die pad and second RDL pad. The first RDL pad includes an RDL notch facing the second RDL trace. Under bump metallization (UBM) pads on a second dielectric include a first UBM pad coupled to the first RDL pad over a second dielectric via. A first metal bonding connector is on the first UBM pad. The first UBM pad or first metal bonding connector overhangs the first RDL pad over the notch.

Abstract: Systems and methods for power line transmission are disclosed in which transmitters and receivers are connected to one or more phases of the power line. At least one symbol stream to be transmitted on the power line network is generated. The at least one symbol stream is scaled using a weight vector to generate a plurality of scaled symbol streams. The weight vector comprises a plurality of weights, each corresponding to a phase of the power line network. Each of the scaled symbol streams are transmitted on a corresponding phase of the power line network. A zero crossing detector identifies phase information for a receiver. A concentrator adapts signals to be sent to the receiver based upon the phase associated with the receiver.

Abstract: A device manages data for a digital signal processor. The device includes an external random access memory (RAM), configured to store channel specific data for plural different channels; and a microprocessor, in communication with the external RAM. When receiving the packet, in a transport layer processing the packet, the microprocessor determines a channel of the plural different channels corresponding to an indication in a transport layer header of the received packet. The microprocessor fetches channel specific data specific to the channel into an internal memory internal to the microprocessor from the external RAM, by the transport layer, before the packet is passed to an application layer, thereby avoiding a wait for reading the packet at the application layer.

Abstract: Apparatus and methods disclosed herein operate to determine a base oscillator frequency and a frequency conversion factor associated with a radio receiver local oscillator (LO). Base oscillator frequency and frequency conversion parameters are selected such that spurious harmonics created within the LO lie outside of communication bands associated with other active radio receivers substantially collocated with the LO. An LO chain including the appropriate base oscillator and frequency conversion components is selected from a switched set of base oscillator/frequency converter pairs.

Abstract: A semiconductor device without cantilevered leads uses conductive wires (120) to connect the chip terminals to the leads (110), and a package compound (140) to encapsulate the chip surface (101a) with the terminals, the wires, and the lead surfaces with the attached wires. The chip surface (101b) opposite the terminals together with portions (103) of the chip sidewalls protrude from the package, allowing an unimpeded thermal contact of the protruding chip surface to a substrate (201) to optimize the thermal flux from the chip to the substrate. Solder bodies (250) attached to the compound-free lead surfaces (113b) can be connected to the substrate so that the solder bodies are as elongated as the protruding chip height, facilitating the void-free distribution of an underfill compound into the space between chip and substrate, and improving the absorption of thermomechanical stresses during device operation.

Abstract: A method for building a look-up table for a receiver in a multiple-input multiple-output (MIMO) detection system simulates a MIMO detector over many channel realizations, tracks channel metric and parameter values used for each channel realization resulting from such simulating, and stores, in a look-up table, best values of the tracked values used for a particular channel metric.

Abstract: A method consisting of determining, by a symbol mapper, whether a previous burst position is below a threshold, wherein the previous burst position defines a location within a previous symbol. A determination that the previous burst position is below the threshold causes generating, by the symbol mapper, a random number in a complete set, the random number defines a current burst position, the current burst position defines a location within a current symbol and sending or receiving a value in the current burst position. A determination that the previous burst position is above the threshold causes generating, by the symbol mapper, a random number in a reduced set, the random number defines a modified current burst position, the modified current burst position defines a location within the current symbol and sending or receiving a value in the modified current burst position.

Abstract: A set of parameter drifts is recorded over a period of time for each of a series of stress tests on a system at various stress levels. Each set of the recorded parameter drifts is plotted as parameter drift versus time. The plots are then time shifted in relation to a reference plot to form a single parameter drift plot. A non-linear equation is fitted to the single parameter drift plot and then used to predict parameter drift over the life of the system. The non-linear equation may be modified by adding a stress acceleration factor to allow prediction of parameter drift over time at different stress levels.

Abstract: Disclosed herein is a method of manufacturing a semiconductor package with a solder standoff on lead pads that reach to the edge of the package (non-pullback leads). It includes encapsulating a plurality of die on a lead frame strip. The lead frame strip comprises a plurality of package sites, which further comprises a plurality of lead pads and a die pad. The method also includes forming a channel between the lead pads of nearby package sites without singulating the packages. Another step in the method includes disposing solder on the lead pads, the die pad, or the lead pads and the die pads without substantially covering the channel with solder. The manufacturing method further includes singulating the packages.

Abstract: A method and system for reduced feedback transmit beamforming computes a matrix of channel transfer function coefficients. The matrix of channel transfer function coefficients is compressed by applying a rotation matrix having orthogonal columns to the matrix of channel transfer function coefficients to produce a compressed transfer function matrix having a reduced number of non-zero coefficients. The compressed matrix is fed back to a transmitting unit. Decompression of the transfer function coefficient matrix is not required. This compression does not cause any performance degradation for transmit beamforming. The transmitting unit computes a set of beamsteering coefficients from the compressed matrix and applies the coefficients to signals prior to transmission. The beamformed signals are transmitted to the receiving unit and post-coded to allow the receiving unit to see an effective diagonalized channel.

Abstract: A method of performing overlap-and-add length for zero-padded suffixes. The method includes derotating received information symbol samples. The derotated received information symbol samples include a first set of derotated received information symbol samples and a second set of derotated received information symbol samples. The first set of derotated received information symbol samples are stored in a buffer. The second set of derotated received information symbol samples are provided to a received sample processing unit. The received zero-padded suffix samples are deroted. Based upon an overlap-and-add length, at least a fraction of the derotated received zero-padded suffix samples is added with at least a fraction of the first set of derotated received information symbol samples to produce multiple summed samples. The multiple summed samples is provided to the received sample processing unit.

Abstract: A method for fabricating integrated circuit (ICs) having through substrate vias (TSVs) includes forming active circuit elements on a semiconductor wafer and then forming a plurality of embedded vias through the top side of the wafer. A metal filler layer including a filler metal is deposited to fill the embedded vias. Chemical mechanical polishing (CMP) then forms a plurality of embedded TSVs that have polished top TSV surfaces having exposed filler metal. An electrically conductive hillock suppression structure is formed by forming a silicon or germanium doped region, or a silicide or germanicide at the polished top TSV surface or by forming a metal layer on the polished top TSV surface having a composition different from the filler metal. A dielectric layer is deposited on the semiconductor wafer including over the hillock suppression structure. The dielectric layer is removed over the polished top TSV surface to allow metal contact thereto.

Abstract: In at least some disclosed embodiments, a system includes a Viterbi decoder and predecoding logic coupled to the Viterbi decoder. The predecoding logic decodes encoded data. The system further includes detection logic coupled to the predecoding logic. The detection logic tests decoded data, and the detection logic produces a binary result. The Viterbi decoder is enabled if the binary result is a first value, and the Viterbi decoder is disabled if the binary result is a second value.

Abstract: Authentication methods are provided that allow for superior security, power consumption, and resource utilization over existing authentication methods. By computing only two hashes of a shared secret password for each protocol run, the methods described in this disclosure dramatically reduce the computational power needed to perform authentication. Similarly, by exchanging these hashes bitwise or piecewise for verification, rather than performing new hashes including each bit of the password separately, the methods described in this disclosure reveal less information about the password being authenticated than existing methods. The methods described in this disclosure also allow for authentication using fewer messages and with lower latency, reducing the amount of operational power used in the authentication process.

Abstract: A method of forming integrated circuit (IC) die configured for attachment to another die or a package substrate, and stacked IC devices therefrom. At least one IC die having a top semiconductor surface and a bottom surface and at least one through substrate via (TSV) including a tip protruding beyond the bottom surface to a tip length is provided. The tip has an outer dielectric tip liner, and an electrically conductive portion within the outer dielectric tip liner. A compliant layer is applied to the bottom surface of the IC die. The dielectric tip liner is removed from a distal portion of the tip to expose an electrically conductive tip portion. A solder material is deposited on the exposed distal portion of the tip. The solder material is reflowed and coalesced to form a solder bump on the distal portion of the tip.

Abstract: A level formatter is provided that has differentially coupled closed loop current sources, each configured to precisely establish a current proportional to a reference voltage. A bridge circuit is differentially coupled to two supplementary current sources and controlled to rapidly switch the current from the supplementary current sources to produce output voltages at respective outputs that are approximately equal to respective one of two reference voltages.

Abstract: A ball grid array device with an insulating substrate (110) having metal traces (106, for example copper, about 18 ?m thick) with sidewalls (108) at right angles to the trace top. The traces are grouped in a first (120) and a second set (121). The first set traces have the top surface covered by a thin noble metal (for example a nickel layer (130) about 0.1 ?m thick and an outermost gold layer (131) about 0.5 ?m thick), while the sidewalls are un-covered by the noble metal. About 1.5 ?m are thus gained for the trace spacing; oxidation of the trace sidewalls is enabled. The second set traces have the top surface un-covered by the noble metal; the traces are covered by an insulating soldermask. A semiconductor chip (101) with terminals (102) is attached to the substrate with the terminals connected to the noble metal of the first set traces, either by bonding wires (for example gold) or by metal studs (for example gold).