Abstract: A module board has trace impedances that are matched at trace junctions. An input line that drives a signal to a junction has its impedance adjusted to match the equivalent impedance of branch traces output from the junction. Since input and output impedances match, reflections caused by the junction are minimized or eliminated. The input impedance can match by being within 20% of the equivalent impedance of the branch lines. The equivalent impedance of branches is the reciprocal of the sum of the individual branch lines' reciprocal impedance. Termination can be eliminated when such junctions are impedance-matched. Secondary junctions can also be impedance-matched, allowing for a variety of trace topologies. Such trace-impedance matching is especially useful for memory modules.

Abstract: A symmetric dual-voltage charge pump and its control circuit generate bipolar output voltages. The charge pump converts a unipolar power source to a set of dual-voltage outputs of opposite polarity that are completely independent of each other. The charge pump includes two voltage-boosting transfer capacitors and two output capacitors. Two-phase operation generates an increased-magnitude output voltage of a negative polarity and another two phases of operation generate an increased output voltage of a positive polarity. The charge pump selectively charges one or both of the bipolar outputs with individual 2-phase charge cycles or with a sequence of charge cycles. When controlled by comparators with unequal reference voltages, the charge pump can force the bipolar outputs to unequal positive and negative voltages. Charge pumping is faster since only 2 phases are needed for charging either the positive or negative output.

Abstract: An environmental tester for memory modules has an environmental chamber for heating the memory modules being tested. One side of the chamber is a backplane. The memory modules are inserted into sockets on module motherboards, which are inserted into motherboard sockets on the backplane. On the other side of the backplane, card sockets receive pattern-generator cards that are outside the environmental chamber but electrically connected to the module motherboards through the backplane. The pattern-generator cards contain pattern-generators that generate address, data, and control signals that exercise the memory modules. The pattern-generator cards can be cooled while the memory modules in the environmental chamber are heated. Pattern-generator cards can be removed for repair and module motherboards can be removed for inserting new memory modules for testing.

Abstract: A network switch routes switch packets among nodes with input and output ports. The nodes are connected together in a loop by two buses. One bus sends packets in a clockwise direction around the loop of nodes, while the other bus sends packets in a counter-clockwise direction around the loop. Each bus is divided into links between adjacent nodes, which examine and forward the packets to the next node in the loop. A packet is duplicated and injected onto both buses from a source node, reaching half of the nodes in one direction, and the other nodes in the opposite direction. A distance value in the packet header is set to half of the number of nodes so that the packet is removed after traveling half-way around the loop. A bit-mask in the header indicates nodes to receive the packet, or source-monitoring can remove packets half-way around the loop.

Abstract: A divide by X.5 circuit can be implemented as a divided by 1.5 circuit. A phase-locked loop (PLL) has a quadrature voltage-controlled oscillator (VCO) that generates four phases offset at 0, 90, 180, and 270 degrees. Differential signals from the VCO are converted to single-ended VCO clocks that drive four divide-by-3 circuits, each clocked by one of the four phases of the VCO clocks. Resets to the divide-by-3 circuits are staggered to activate each divide-by-3 circuit synchronously with its phase clock. Outputs from the divide-by-3 circuits are applied to a frequency doubler that generates the final clock that is 1.5 times slower than the VCO clocks. The final clock has a near 50%-50% duty cycle.

Abstract: A flash-drive or flash-card reader connects to a personal computer (PC) through a serial link such as a Universal-Serial-Bus (USB), IEEE 1394, SATA, or IDE. A local CPU acts as the bus master of a CPU bus that connects to slave ports on a flash-memory controller, a serial engine, and a RAM buffer. A second bus in parallel to the CPU bus connects a second slave port on the RAM buffer to a master port on the flash-memory controller and to a master port on the serial engine. The flash-memory controller or the serial engine can use their master ports to transfer data to and from the RAM buffer using the second bus, allowing the CPU to retain control of the CPU bus. The second bus is a flash-serial buffer bus that improves data transfer rates. The flash-memory controller can prefetch into the RAM buffer.

Abstract: Transistors with very thin gate oxides are protected against oxide failure by cascading two or more transistors in series between an output pad and ground. The intermediate source/drain node between the two cascaded transistors is usually floating during an ESD test, delaying snapback turn-on of a parasitic lateral NPN transistor. This intermediate node is used to drive the gate of an upper trigger transistor. A lower trigger transistor has a gate node that is charged by the ESD pulse on the pad through a coupling capacitor. When the coupled ESD pulse turns on the trigger transistors, the trigger transistors turn on a silicon-controlled rectifier (SCR) that is integrated with the trigger transistors.

Abstract: A multi-attribute trading system creates value for both the buyer and seller. A spread or net value between the buyer's true value and the seller's true value is divided among the buyer, seller, and trading system. Multiple true values are inputted by a buyer for products with varied attribute specifications such as travel services. These multiple values are stored in a buyer attribute tree. Likewise, the seller specifies multiple true values for a multi-attribute product that are stored in a seller attribute tree. The trading system compares the buyer attribute tree to the seller attribute tree. For each specification of the multiple attributes, the spread or difference between the buyer-specified true value and the seller-specified true value is calculated. The attribute specification producing the maximum of these spreads is selected for trading.

Abstract: A phase-locked loop (PLL) has an analog divider in the feedback path that receives either the in-phase or quadrature-phase pair of outputs from a voltage-controlled oscillator (VCO) while the other pair, 90-degree out-of-phase, of outputs from the VCO is used for the PLL output. Phases between the PLL's input and output are inherently aligned. The analog output of the analog divider is converted to a digital clock signal and applied to a cascade of digital dividers to generate a reduced feedback clock. The reduced feedback clock is applied to the D input and the digital clock signal is applied to the clock input of a pseudo D-flip-flop that drives the feedback input of a phase-frequency detector that drives the charge pump to the VCO input. Another cascade of digital dividers and pseudo D-flip-flop re-align the reference clock input to the phase-frequency detector. Analog and digital re-alignment circuits reduce internal skew.

Abstract: A slim Universal-Serial-Bus (USB) connector fits on only one side of the connector substrate in a standard female USB connector. Wobble or vertical play is reduced by locking depressions in the slim USB connector that engage metal springs on a metal case that surrounds the female USB connector, locking the two connectors together. Between metal contacts on the slim USM connector are dividers that help fill in gaps when the two connectors are connected together, further reducing play. End rails on the slim USB connector fill in gaps on the sides. The connector substrate of the slim USB connector can be separate or can be integrated with a circuit board that holds a flash memory chip and a USB controller chip. The connector is wider than the standard width for a better fit. A slim female USB connector for use with the slim male USB connector is also disclosed.

Abstract: A register chip for double-data-rate (DDR) memory modules operates in 1:1 mode or 1:2 mode. A differential input clock is buffered to generate a slave clock that continuously clocks slave stages of flip-flops, and gated to generate a first clock pulsing only in 1:1 mode and a second clock pulsing only in 1:2 mode. The master stage has two input transmission gates, one activated by the first clock and another activated by the second clock. In 1:1 mode a first data bit is sampled by the first clock, but in 1:2 mode a second data bit is sampled by the second clock. The sampled bit is inverted and applied to the slave stage and to a feedback gate that has transistors gated by the first and second clocks. The clock-to-output delay is improved since an output mux is replaced by the muxing function built into the master stage.

Abstract: A differential input buffer shows reduced sensitivity to input conditions such as input-trace loading and upstream driver characteristics. Varying input conditions can be measured as differences in amplitude, slew rate, and common-mode offset. Wide input-voltage swings are clamped to a limited voltage range by an input clamp circuit that uses source followers to drive p-channel clamp transistors that turn off when the input voltage is too low. A voltage divider then sets the lowest voltage input to a differential stage. The differential stage receives the clamped inputs and has two tail current sinks to reduce delay sensitivity to charging and discharging of tail capacitances. A middle voltage is applied to transistors opposite the differential transistors that receive the clamped input voltages. A bias voltage for the tail current sinks is generated by mirroring currents and setting a gate voltage by injecting and removing a same bias current from a resistor.

Abstract: A voltage-variable capacitor uses the channel-to-substrate junction from a gated diode formed from a metal-oxide-semiconductor transistor. The transistor gate has at least two contacts that are biased to different voltages. The gate acts as a resistor with current flowing from an upper gate contact to a lower gate contact. The gate-to-source voltage varies as a function of the position. A critical voltage is where the gate-to-source voltage is equal to the transistor threshold. A portion of the gate that has gate voltages above the critical voltage has an inversion layer or conducting channel under the gate. Another portion of the gate has gate voltages below the critical voltage, and thus no channel forms. By varying either the gate voltages or the source voltage, the area of the gate that has a channel under it is varied, varying the channel-to-substrate capacitance. Separate gate arms reduce bias current.

Abstract: A power-down mode is activated when equal voltages are detected on a pair of differential inputs. The voltage difference across the differential inputs is applied to a multiplier, which generates a squared difference. The squared difference is smoothed and filtered by a low-pass filter to produce an average signal. The average signal is compared to a reference voltage, either explicitly or implicitly, to detect when the voltage difference across the differential inputs is too small. A power-down signal is activated when the average signal is too small. The multiplier can be implemented with a Gilbert cell, while a filter-comparator converts the differential Gilbert-cell output to a single-ended signal and filters the signal. The reference voltage compared can be set by the switching threshold of the filter comparator or other logic gates. A complementary Gilbert cell and filter-comparator can be used to increase the operating range.

Abstract: Gamma correction or other power functions are generated for correcting the light intensity for digital pixels. Two levels of mapping of segments are preformed to reduce the total number of segments for a given precision. The range of inputs is divided into successively smaller segments. Each segment is smaller than the next by a factor of 1/a for a first or primary level, or 1/b for a second level of segments. All inputs are mapped or scaled up to the input range of the largest segment in the primary level. Then the largest primary segment is further divided into several second-level segments, and the input is again mapped or scaled into the largest of the second-level segments. Gamma correction is performed on the input scaled into the largest second-level segment. A linear approximation within the largest second-level segment is used.

Abstract: Presence or absence of a differential clock is detected. The voltage of each differential clock line is compared to the common-mode voltage and integrated over time by a capacitor. The capacitor is discharged during the portions of the clock cycle that the differential line is over the common-mode voltage. If the clock stops pulsing the capacitor is charged by a current source to activate a clock-loss signal. The clock-loss detector is ideal for high-frequency operation since each differential clock line is applied to only one transistor gate. The common-mode voltage generates a bias voltage for a differential amplifier that receives the true and complement differential clock lines. Diodes prevent capacitor charging by reverse current flow from the differential amplifier when the clock is inactive. The averaged peak voltage or envelope of the differential input signals is detected.

Abstract: An error-resilient decoder for motion-picture-experts group (MPEG-4) video detects variable-length resync markers together with video packet (VP) headers at the start of each video packet in a video object plane (VOP). An f_code in the VOP header indicates a motion-vector search range and a bit length for all resync markers in the VOP. When the f_code is correctly read, the bitstream is searched for a fixed-length resync markers. However, when an error occurs in this f_code, the length of the resync markers is unknown. A multi-pattern resync marker and VP header decoder searches the bitstream for one of 7 patterns for each possible resync marker bit-length. A match allows the VP header and data to be decoded even when bit errors occur in the VOP header. Faster recovery occurs for corrupted bitstreams such as those transmitted over wireless networks.

Abstract: A production test machine pre-screens panels of memory modules for shorts and leakage and other D.C. parameters. Memory modules are constructed as part of a panel of 6 or so modules formed on the same substrate. The modules are connected together by links of the substrate. The D.C. tests are performed on memory modules before separation from the panel (de-panelization), while the modules are still connected together by the panel links. Using parallel testing, a whole panel of modules can be D.C. tested at the same time. Failing modules can then be marked or noted, and the good modules separated from the panel links and sent to a more expensive A.C. tester for functional testing. The spacing or pitch of test heads on the D.C. tester can be adjusted for different sizes of panels.

Abstract: A phase-locked loop (PLL) keeps tracking a reference clock when a frequency offset is introduced. The PLL has primary and secondary PLL loops. A digital-to-analog converter (DAC) generates a current that is passed through an offset resistor to generate an offset voltage. An op amp is inserted in the primary loop between a filter capacitor and a voltage-controlled oscillator (VCO). The offset resistor is coupled between the inverting input of the op amp and the op amp's output. When the DAC offset occurs, the voltage to the VCO and the frequency of the primary loop change and the primary loop loses tracking of the reference clock. The secondary loop keeps tracking the reference clock during the DAC offset while the primary loop is open. Then the output clock of the secondary loop is applied as the feedback clock to the phase comparator of the primary loop.

Abstract: An amplifier drives a Digital-Subscriber Line (DSL) using a 12-volt power supply. Ordinary low-voltage transistors for 5-volt systems are stacked together to reduce the average voltage across each transistor to below a breakdown voltage. The output stage uses p-channel and n-channel driver transistors that are coupled to differential outputs through cascode transistors. A common-mode voltage is fed back to a second stage to adjust signals for deviations in the common-mode output bias. A first stage buffers a pair of differential inputs to the second stage. The second stage uses level shifting to generate four signals to the output stage driver transistors. A pair of high-voltage signals drives the p-channel drivers while a pair of low-voltage signals drives the n-channel driver transistors. Nested miller compensation stabilizes the amplifier using capacitors between the final outputs and the four signals from the second stage and the differential signals from the first stage.