Abstract: A graphics controller for a System-On-a-Chip (SOC) used with a battery-powered device allows for reduced-power display modes. The microprocessor writes to a frame buffer that is a single, contiguous address block in virtual memory. A memory management unit (MMU) translates frame-buffer address to multiple physical blocks. The graphics controller fetches pixels from the multiple physical blocks, including a block in an on-chip memory and a block in an external memory. In a low-power mode, pixels are only fetched from the lower-power on-chip memory and not the higher-power external memory. A smaller display window is defined and pixels outside the window are replaced by dummy data,.eliminating external-memory fetches. The smaller display window falls within the first block in the on-chip memory. Status and other information can be displayed in the smaller display window during stand-by modes, while a full-screen of data is displayed for full-power modes.

Abstract: A power-down signal is encoded into a differential pair of lines between two chips. When the differential transmitter powers down, it enters a high-impedance state and floats the differential lines. A shunt resistor between a pair of differential lines equalize the voltages on the differential lines so they float to a same voltage when a differential transmitter is disabled and enters a high-impedance state. The condition of equal voltages on the differential lines is detected by an equal-voltage detector that generates a power-down signal when the differential lines are at equal voltages for a period of time. The period of time can be greater than the cross-over time during normal switching to prevent false power-downs during normal switching. Standard differential drivers can signal power-down using the high-impedance state, which is detected by equal voltages on the differential lines. A sensitive dual-differential amplifier and a simpler detector are disclosed.

Abstract: A voltage-variable capacitor uses the channel-to-substrate junction from a gated diode formed from a metal-oxide-semiconductor transistor. The transistor gate has at least two contacts that are biased to different voltages. The gate acts as a resistor with current flowing from an upper gate contact to a lower gate contact. The gate-to-source voltage varies as a function of the position. A critical voltage is where the gate-to-source voltage is equal to the transistor threshold. A portion of the gate that has gate voltages above the critical voltage has an inversion layer or conducting channel under the gate. Another portion of the gate has gate voltages below the critical voltage, and thus no channel forms. By varying either the gate voltages or the source voltage, the area of the gate that has a channel under it is varied, varying the channel-to-substrate capacitance. Separate gate arms reduce bias current.

Abstract: A bus switch has a p-channel and an n-channel transistor in parallel between two buses. When power is disconnected to the bus switch, and one bus is hot and has a voltage above ground, this higher voltage is conducted to the gate and substrate of the p-channel transistor. This biasing keeps the p-channel transistor turned off. A gate connecting p-channel transistor connects the hot bus to the p-channel gate node, while a substrate connecting p-channel transistor connects the hot bus to the substrate under the p-channel transistor. A third connecting p-channel transistor connects the hot bus to a power-down node. The power-down node is normally driven low through a delay line when power is applied. The power-down node is applied to the gate of a source transistor that connects power to the substrate and to an inverter that normally drives the p-channel gate node.

Abstract: A fail-safe circuit for a differential receiver can tolerate noise. A latch is enabled when both differential inputs V+, V− rise above a reference voltage that is close to Vcc. The latch, once enabled, is set by an offset amplifier, signaling the fail-safe condition. The offset amplifier sets the latch when V+ is above or equal to V−. The differential amplifier has a small offset voltage to allow the latch to remain set when V+ and V− are equal in voltage. An output from a differential amplifier receiving V+ and V− can be blocked by a gate when the fail-safe condition is latched. Pullup resistors pull V+, V− to Vcc when an open failure occurs. The latch remains set when common-mode noise occurs on V+, V−, preventing noise from prematurely disabling the fail-safe condition. Such noise coupled into a broken cable is usually common-mode.

Abstract: A digital-camera processor receives mono-color digital pixels from an image sensor. Each mono-color pixel is red, blue, or green. The stream of pixels from the sensor has alternating green and red pixels on odd lines, and blue and green pixels on even lines in a Bayer pattern. Each mono-color pixel is white balanced by multiplying with a gain determined in a previous frame and then stored in a line buffer. A horizontal interpolator receives an array of pixels from the line buffer. The horizontal interpolator generates missing color values by interpolation within horizontal lines in the array. The intermediate results from the horizontal interpolator are stored in a column buffer, and represent one column of pixels from the line buffer. A vertical interpolator generates the final RGB value for the pixel in the middle of the column register by vertical interpolation. The RGB values are converted to YUV. The vertical interpolator also generates green values for pixels above and below the middle pixel.

Abstract: Electro-static-discharge (ESD) protection of an integrated circuit chip is enhanced by an EOS protection circuit using external components. An external MOSFET is placed in series with the ground pin of the integrated circuit chip. The external MOSFET has a gate coupled to a power bus through a gate resistor, and is bypassed by an ESD capacitor. The external MOSFET turns on after a delay when power is applied during hot insertion. The delay is determined by a power-to-ground bypass capacitor. The time delay of the on stage of the MOSFET inhibits ground current generated by EOS voltage leaked from the power supply through parasitic resistances, capacitances, and inductances, preventing ESD-protection diodes inside the chip from burning out from this EOS pulses that occur during hot insertion. The ESD bypass capacitor shunts the initial ESD pulse to ground before the external MOSFET turns on.

Abstract: Electronic mail (email) is certified and authenticated by an authentication service. The authentication service is integrated with an email web site that allows users to set up email accounts. Outgoing email from the email web site is routed to the authentication service. A message identifier (ID) is generated and added to the message within markers. A random-number generator creates random pad characters that are added to the message before a checksum is generated. The checksum and the pad characters are stored in a table indexed by the message ID. The pad characters and the checksum are placed in secure storage and not available to users or others on the Internet. The email with the message ID in the markers but without the pad characters or checksum is sent to the recipients, along with instructions on how to authenticate the message. Others can authenticate a message by emailing it to the authentication service.

Abstract: A voltage-controlled crystal oscillator (VCXO) has variable load capacitors on the crystal nodes. The variable load capacitors are p-channel or n-channel transistors with their source and drain nodes connected to a crystal node. The gates are driven by an input voltage that is generated from a full-swing control voltage by a voltage conversion circuit. The input voltage has a half-swing of only half of the power-supply voltage, or VDD/2. The input voltage driving n-channel capacitors swings from VDD to VDD/2, which is just above the source voltage of VDD/2 on the crystal node and ensures that the n-channel capacitors remain on for most of the range. A series of resistors can divide the input voltage into a series of differing voltages that drive gates of multiple n-channel capacitors that have their source/drains connected in parallel to the crystal node. Capacitance increases as an n-channel capacitor channel turns on.

Abstract: A digital-camera processor receives a stream of mono-color pixels in a Bayer pattern from a sensor. Two lines of the pattern are stored in a 2-line buffer. Red, Blue, and Green interpolators receive a 3×3 array of pixels from the 2-line buffer. The interpolators generate missing color values by interpolation. For green, horizontal interpolation is performed for odd lines, while vertical interpolation is performed for even lines. Horizontal and vertical interpolation is thus alternated with alternate lines. Edge detection is performed at the same time as interpolation, on the green pixels from the 2-line buffer. An edge-detection filter is multiplied by the green pixels in the 3×3 array from the 2-line buffer. Different edge-detection filters are used for odd and even lines. These filters are modified to detect edges running perpendicular to the direction of the green interpolation filter. Edges in the same direction as the interpolation filter are ignored.

Abstract: An interconnection network routes packets among switches connected in a multi-dimensional network of links. Each packet contains a header with an address of a source switch connected to an input port that receives the packet, and a destination switch connected to an output port that transmits the packet. Each packet header also contains a random address of a random switch in the network. The packet is first routed from the source switch toward the random switch. Then a phase flag in the header is cleared by the random switch, and the packet is routed toward the destination switch. If a faulty link or switch is encountered, and no known routes are available to the destination, the phase flag is again set and another random address generated. The packet is then routed to a new random switch, bypassing the fault.

Abstract: A power-down signal is encoded into a differential pair of lines between two chips. When the differential transmitter powers down, it enters a high-impedance state and floats the differential lines A shunt resistor between a pair of differential lines equalize the voltages on the differential lines so they float to a same voltage when a differential transmitter is disabled and enters a high-impedance state. The condition of equal voltages on the differential lines is detected by an equal-voltage detector that generates a power-down signal when the differential lines are at equal voltages for a period of time. The period of time can be greater than the cross-over time during normal switching to prevent false power-downs during normal switching. Standard differential drivers can signal power-down using the high-impedance state, which is detected by equal voltages on the differential lines. A sensitive dual-differential amplifier and a simpler detector are disclosed.

Abstract: An incrementer pipelines the generation of carry lookahead signals. Count registers hold a current count of the incrementer. The current count is fed back as inputs to sum logic, which generates sum bits that are latched into the count registers as a next count. All-ones detect logic detects when all lesser-significance bits in the current count are ones. When all lesser bits are ones, the sum logic toggles the count bit to generate the sum bit for that bit position. Pre-carry logic generates pre-carry lookahead signals from the sum bits. The pre-carry lookahead signals are latched into pipelined carry registers. The pipelined carry registers drive pipelined carry lookahead signals to the all-ones detect logic. Thus carry lookahead signals are generated from a prior sum but used in a next clock cycle to generate then next sum.

Abstract: A differential output buffer has a primary stage and a secondary stage that each directly drive differential outputs. Link transistors between the secondary stage and the differential outputs are eliminated. The primary stage continuously receives differential inputs applied to gates of n-channel sourcing and sinking transistors. The sources of the sourcing transistors and the drains of the sinking transistors are connected to the true and complement differential outputs. The secondary stage also has n-channel sourcing and sinking transistors directly connected to the differential outputs. Pulsed inputs applied to secondary-stage gates are normally low, disabling the sourcing and sinking transistors in the secondary stage to disable the secondary stage. However, during a switching transient, the pulsed inputs are pulsed on, allowing the secondary stage to drive a boost current to the differential outputs.

Abstract: An optimal path through the Internet to a client is determined by the server during connection establishment. During the 3-way handshake that establishes a connection, a web server ordinarily sends a single SYN+ACK packet to the client. Instead of sending just one SYN+ACK packet, the server is modified to send multiple SYN+ACK packets, each using a different path to the client. When the multiple SYN+ACK packets are sent from the server at the same time, the first packet that reaches the client used the fastest path through the Internet. The client responds to this first SYN+ACK packet with an ACK packet back to the server. The other SYN+ACK packets that use slower paths arrive at the client after the first SYN+ACK packet and are ignored by the client as being out-of-order. The server includes a different sequence number with each SYN+ACK packet. The client increments this sequence number and includes the incremented sequence number in the ACK packet.

Abstract: A differential clock driver uses feedback to reduce timing skews between the true and complement differential outputs. Each of the differential outputs has a pull-up driver and a pull-down driver. Each pull-up or pull-down driver has an initial transistor and a final transistor in parallel to drive the output. A resistor separates gates of the initial and final transistors, causing a delay to enable the final transistor. A transmission gate provides feedback from the other output to the gate of the final transistor. When the other output is faster that the output being driven, the transmission gate transfers charge from the other output to the gate of the final transistor, causing it to speed up driving its output. This helps compensates for the timing skew between the outputs. Skews present on differential inputs can be compensated by the transmission gate feedback.

Abstract: A clock driver chip has several banks of clock outputs driven by a single clock reference. Each clock output is driven by large pull-up and pull-down transistors, which have gates driven by pre-driver lines generated by a pre-driver circuit. Individual clock outputs, or a bank of outputs, are enabled by enable signals. A shorting switch is activated when enables for a pair of clock outputs are in a same state. The shorting switch has two transmission gates. One transmission gate shorts the pre-driver lines to the large p-channel transistors of the pair of outputs, while the other transmission gate shorts the pre-driver lines to the large n-channel transistors of the pair of outputs. Pre-driver lines to the pull-up transistors within a bank driven by the same enable can be hardwired together, as can the pre-driver lines to the pull-down transistors. Shorting switches can short banks together to reduce output skew.

Abstract: A phase-locked loop (PLL) includes a final mixer on its output. The final mixer subtracts out a noise or error term from the PLL's output to reduce noise and jitter. A first mixer generates the error term by subtracting a feedback clock from the reference clock. This error term is near D.C. since the feedback and reference clocks are at the same frequency. When this error term is subtracted from the PLL output, a secondary maxima in the noise plot at the PLL's loop bandwidth is removed. A feedback counter receives the output of the voltage-controlled oscillator (VCO) before the final mixer. Outer-band noise created by the VCO is subtracted out by the final mixer, using the error term generated by the first mixer. The mixers reduce noise generated by the VCO or from other sources in the PLL.

Abstract: A bus switch is protected from undershoots on either of its terminals. The bus switch transistor is an n-channel metal-oxide-semiconductor (MOS) with its source connected to a first bus and its drain connected to a second bus. During isolation, the gate node of the bus switch transistor is discharged to ground by a pulsed transistor, and then kept at ground by a leaker transistor. Sense-pulse circuits are attached to the first and second bus. When a low-going transition is detected by a sense-pulse circuit, an n-channel connecting transistor is turned on, connecting the bus with the low-going transition to the gate node through a grounded-gate n-channel transistor. If an undershoot occurs, it is coupled to the gate node. Since both the gate and source of the bus switch transistor are coupled to the undershoot, the gate-to-source voltage never reaches the transistor threshold and the bus switch transistor remains off.

Abstract: When the clock is stopped during a power-down mode, a clock duty-cycle detector asserts a power-down signal. The clock input is filtered to produce an average clock voltage over several clock periods. The average clock voltage is compared to an upper reference voltage to determine when the clock's duty cycle (high pulse-width percent) is above an upper limit. The average clock voltage is also compared to a lower reference voltage to determine when the clock's duty cycle is below a lower limit. When the clock's duty cycle is above the upper limit or below the lower limit the power-down signal is activated by logic. The logic disables the power-down signal when the clock's duty cycle is between the upper and lower limits. High-frequency clock glitches do not falsely trigger a power-up, since glitches are usually narrow and not sufficiently wide to reach the lower limit.