Abstract: ESD protection is provided by local ESD-protection devices between each pad and a common-discharge line (CDL). Each ESD-protection device has p-well or p-substrate taps to a local ground rather than to the CDL, reducing noise coupling from the I/O's through the CDL. Another ESD clamp that bypasses the CDL is provided between each pair of internal power and ground buses. Better protection of core circuits during power-to-ground ESD events is provided by bypassing the CDL since only one ESD clamp rather than two ESD-protection devices must turn on. The ESD clamps and ESD-protection devices can be gate-coupled n-channel transistors with coupling capacitors between the pad and the transistor gate. Devices can also be substrate-triggered transistors or active ESD clamps that include an inverter between a coupling capacitor to the CDL and the n-channel transistor gate.

Abstract: A cross-pin electro-static-discharge (ESD) protection device protects against ESD zaps between two I/O pins. Pin A is connected to a drain of a bus-switch transistor and pin B is connected to the transistor's source. An ESD protection device on pin A has an n-channel shunting transistor to an internal ground bus. The gate of the shunting transistor is a cross-gate node that is capacitivly coupled to pin A, and has a leaker resistor to ground. An n-channel cross-grounding transistor has its gate connected to the same cross-gate node, but it connects the internal ground bus to pin B, which is grounded in the pin-to-pin ESD test. An ESD pulse on pin A drives the cross-gate node high, turning on both the shunting transistor and the cross-grounding transistor. The floating internal ground bus is connected to ground by pin B, grounding the substrate of the bus-switch transistor to prevent its turn-on.

Abstract: Multicast is performed in a packet-based network switch having a switch fabric of store-and-forward switch nodes. Congestion and blocking at an ingress port is avoided because packet replication is performed at random nodes dispersed throughout the switch fabric. Each multicast packet inserted into the switch fabric by the ingress port is sent to a randomly-selected node. The random node replicates the multicast packet into many unicast packets that are routed to egress ports. A SONET frame can be divided into several multicast packets that are dispersed to different random nodes before replication, thus dispersing congestion. Replication can be delayed until the next SONET frame to prevent latency build up from propagation delays in the switch fabric. Alternately, the SONET payload envelope pointer can be advanced by the propagation delay. Lookup tables at the random nodes can include a list of destinations so that all the destination addresses do not have to be stored in each multicast packet header.

Abstract: A large network switch has switch elements distributed across several chassis separated by perhaps several hundred meters. A generated sync pulse arrives at different switch elements at different times, creating skew. The latency of data through the network switch is set to match the frame period of SONET frames. SONET frames are adjusted at the ingress ports to align the data pointer to the beginning of the frame. The frame is divided along row boundaries into separate cell-packets that are routed across the switch fabric to the egress port. The packets are held in a buffer at the egress port until the next frame begins with the next sync pulse. Upon receiving the next sync pulse, the frame is transmitted. No pointer adjustment is needed by the egress port. A row number is used as a sequence number for the cell-packet to allow the egress port to re-order the cell-packets when transmitting the frame. Since no pointer manipulation is needed at the egress port, pointer management is simplified.

Abstract: A test system has many motherboards. Each motherboard has a reverse-mounted test adaptor board that contains a test socket. A robotic arm inserts a memory module into the test socket, allowing the motherboard to execute programs to test the memory module. A test chamber surrounds the test socket. Compressed air is regulated and routed to local heaters near each motherboard. The local heaters pass the air over a resistive heating element to heat the air. The heated air is then directed into the test chamber to heat the memory module being tested. A local valve controls the air flow through the local heater. A host computer receives temperature measurements from each test chamber and adjusts the local heater and valve to maintain a desired test temperature. The motherboards can be cooled by cooling fans while the memory modules being tested are heated.

Abstract: A buffer chip clocks data to memories on a memory module. The data-input path to registers or flip-flops on the buffer chip are speeded up by removing muxes on the inputs to the flip-flops. Speeding up the data-input path allows power dissipation to be reduced, since smaller input buffers can be used. Control logic combines chip-select and data-strobe control inputs that prevent clocking of the flip-flops. The control logic outputs a combined strobe signal. Set-reset latches are triggered by the combined strobe signal. The set-reset latches allow the clock to pass through to the flip-flop when the chip-select and data-strobe inputs are both active. The set-reset latches block a rising transition of chip-select and data-strobe inputs from changing the clocks to the flip-flop, thus preventing data-clocking errors.

Abstract: A host writes graphics commands and data to programmable registers through a command FIFO that is read by a graphics controller or BitBlt engine. Rather than write an address and a data value for each register programmed, the host writes one address, one index, and several data values. The address points to an index register. The index is a mapping index word with several multi-bit mapping fields. Each multi-bit mapping field in the index identifies a register to be programmed with one of the data values. Since N bits are used for each mapping field, the mapping field can select one register in a bank of 2N−1 registers. The registers in the bank can be programmed in any order, and registers can be skipped. Since only one index is stored in the command FIFO for programming several registers, less memory space and fewer bus cycles are required.

Abstract: A bus-switch transistor connects two I/O pins when an enable signal on its gate is activated. Each pin has an electro-static-discharge (ESD) protection devices. When the internal ground and the enable are floating, and an ESD pulse is applied between the two pins, an isolation circuit couples part of the ESD pulse to the gate of the bus-switch transistor, keeping the transistor turned off. This forces the ESD pulse to travel through the ESD protection devices, preventing damage to the bus-switch transistor. The isolation circuit has a capacitor between a pin and the gate of a coupling transistor. The capacitor couples the ESD pulse to the gate of the coupling transistor. The coupling transistor turns on, connecting the pin to the gate of a grounding transistor. The grounding transistor then turns on, connecting the gate of the bus-switch transistor to the other pin, which is grounded during the ESD test.

Abstract: A decoder for motion-picture-experts group (MPEG-4) video detects start codes at the beginning of video object planes (VOP) and resync markers at the start of each video packet (VP) in the VOP. When an error occurs in the bitstream, a parser searched for a next start code or resync marker to find the start of the next video packet. A partial match of the unique start-code bit sequence signals a fuzzy match, allowing the VOP header and data to be decoded even when bit errors occur in the VOP start code. A fuzzy match of the shorter resync marker can also be enabled. Fuzzy matching of VOP start codes and resync markers allows for faster recovery from corrupted bitstreams such as those transmitted over wireless networks.

Abstract: A bi-directional bus-interface chip has no direction-control input. A forward buffer and a reverse buffer are both normally disabled in the high-impedance state. When a transition occurs on one input bus, a driver transistor in the forward or reverse buffer is activated to pass the transition through the bus-interface chip. After a delay, the driver transistor is disabled. An optional bus-hold circuit maintains voltage levels on buses when driver transistors are disabled. The delay can be selectable by shorting delay resistors in the delay circuit. The high-level voltages on the two busses may differ. The bus-interface chip converts one voltage domain to another and can re-generate weak signals. A pre-buffer may be added to gradually step up the voltage level when differences in voltage domains are large.

Abstract: Pin-to-pin electro-static-discharge (ESD) protection is provided for a bus-switch transistor that is connected to I/O pins at its source and drain. A p-type substrate is normally pumped below ground by a substrate bias generator when power is applied. However, during a pin-to-pin ESD test, power and ground are floating. A gate node is pulled high through a coupling capacitor by the ESD pulse. The gate node turns on a shunting transistor to couple the ESD pulse to the floating ground bus. The gate node also turns on a shorting transistor that connects the floating ground bus to the floating substrate. A resistor drains the coupling capacitor to the substrate, rather than to ground. Current is injected into the substrate by the resistor. The snapback voltage is lowered by substrate-triggering.

Abstract: Error detection is added to a motion-picture-experts group (MPEG) decoder by checking each 8×8-pixel block for constraints. The constraints are added during compression by adjusting discrete cosine transform (DCT) coefficients in the block to meet a constraint. When the decoder determines that the constraint is not met by the DCT coefficients, an error is signaled for that block. The error can then be concealed using pixels from another frame or block. In one embodiment, the constraint is that the last two non-zero coefficients have the same magnitude. The constraint is added during compression after quantization but before variable-length coding by averaging the magnitudes and using the average magnitude for the last two non-zero coefficients. This minimizes visible distortion caused by the constraints and reduces computations.

Abstract: An adaptive color enhancer applies different scale factors to different pixels in a digital image. More color enhancement occurs for bright pixels and for dim pixels than for average-intensity pixels. Also, more color enhancement is applied to the more colorful pixels while less color enhancement is applied to dull, less-colorful pixels. Rather than enhance all pixels to the same extent, the bright, colorful pixels are enhanced further than the average. Likewise, dim areas are color enhanced more than average. A calculation unit receives a YUV pixel. The Y value is compared to range limits and a piece-wise-linear (PWL) function generates an intermediate scale factor. The absolute values of the U and V color values are combined to create a colorfulness factor. The colorfulness factor is also used with a PWL function and the intermediate scale factor to generate a final scale factor for that pixel. The final scale factor is then multiplied by the U and V values of the pixel to generate a color-corrected pixel.

Abstract: Errors are detected in a motion-picture-experts group (MPEG) bitstream that has been corrupted by wireless transmission. Some 16×16 pixel macroblocks are divided into four smaller 8×8 blocks. A motion vector is encoded for each block. The Euclid distance is generated for each possible pair of the four motion vectors, and the maximum of these distances is compared to a threshold distance. When the maximum distance among the motion vectors in a macroblock exceeds the threshold, a bitstream error is signaled and error concealment is triggered. Since the four blocks within a macroblock usually stay close to each other in adjacent video frames, large jumps in the relative location of one block usually indicate a bitstream error. Squares of the distances can be generated and compared to reduce the computational load by eliminating square-root operations.

Abstract: A production test machine pre-screens panels of memory modules for shorts and leakage and other D.C. parameters. Memory modules are constructed as part of a panel of 6 or so modules formed on the same substrate. The modules are connected together by links of the substrate. The D.C. tests are performed on memory modules before separation from the panel (de-panelization), while the modules are still connected together by the panel links. Using parallel testing, a whole panel of modules can be D.C. tested at the same time. Failing modules can then be marked or noted, and the good modules separated from the panel links and sent to a more expensive A.C. tester for functional testing. The spacing or pitch of test heads on the D.C. tester can be adjusted for different sizes of panels.

Abstract: A clock generator uses two PLL loops and a digital-to-analog converter (DAC) to generate a variable output frequency from a single fixed-frequency reference clock. Each PLL loop receives the reference clock and phase-compares it with a feedback clock. The feedback clock in one loop is slightly faster in frequency than the feedback clock in the second loop. The input voltages to voltage-controlled oscillators (VCOs) in the two loops thus vary slightly. A DAC is connected between the two VCO inputs. The DAC's two reference-voltage inputs are connected to these VCO inputs. The DAC's output voltage is selected from within the voltage range between the two VCO voltages by a digital code-word input to the DAC. The DAC's output voltage is input to a final VCO that generates the variable output frequency. The output frequency is varied by selecting the digital code-word input to the DAC.

Abstract: A voltage booster drives the gate of a bus-switch n-channel transistor to a theoretical maximum of triple the power-supply voltage Vcc. The gate node is first driven to Vcc. Then the back-side of a first capacitor is driven from ground to Vcc, coupling a first voltage boost to the gate node. After a Schmidt-trigger detects the back-side of the first capacitor near Vcc, the back-side of a second capacitor is driven from ground to Vcc. The front-side of the second capacitor is connected to the back-side of the first capacitor. A second voltage boost is coupled across the first and second capacitors to increase the voltage boost of the gate node to near triple Vcc rather than just double Vcc.

Abstract: Edge rates for output driver transistors are increased for slower conditions such as caused by supply-voltage, temperature, and process variations. The edge rates are increased by increasing charging and discharging currents to the gates of the driver transistors. Process-sensing transistors have gates tied to power or ground. Current through the process-sensing transistors changes with supply-voltage, temperature, and process variations. The currents through process-sensing transistors are used to generate process-compensated voltages that bias current sources and sinks to adjust process-dependent currents. Process-independent or fixed current sources and sinks use process-independent reference voltages ultimately generated from reference currents that are not sensitive to process variations. The process-dependent-currents are subtracted from the fixed currents to produce the charging and discharging currents.

Abstract: A multi-port Peripheral Component Interconnect (PCI) bus bridge allows for cascading of PCI buses and reduction of bus loading and traffic. The multi-port PCI bridge has three or more ports that connect to PCI buses. At each destination port, a pair of data FIFOs is provided for each source port, for read and write data. Each destination port has three address FIFOs, one for posted-memory-write (PMW) addresses, another for delayed-transaction-request (DTR) addresses and data, and a third for delayed-transaction-completion (DTC) addresses. An address mux receives addresses from all source ports and combines them into the three address FIFOs. When addresses arrive concurrently, the address mux delays one address until the first address has been written into the address FIFO, and then writes the delayed address. Since separate data FIFOs are used for each source port, data is not delayed. Concurrent transactions from different source ports to the same destination port can occur.

Abstract: A transmission line is terminated by a buffer. The buffer isolates a load from the transmission line using a transmission gate. The transmission gate is turned off and does not conduct most of the time, but turns on when a transition is detected on the transmission line, allowing the transmission line to directly drive the load for a short time. Once the load is switched beyond a logic threshold voltage, the transmission gate is again turned off and a latch or latching transistors driven by the transmission line continue to drive the isolated load to power or ground voltages. Driver transistors are also enabled when the transmission gate is turned on, driving either the output (load) node or the input (transmission line) node with the new data. Feedback from the output node disables the transmission gate and driver transistors once the output has been driven past the logic threshold.