Patents Represented by Attorney, Agent or Law Firm Suiter & Associates PC
  • Patent number: 6486712
    Abstract: A programmable switch includes at least one or more pass transistors having a control voltage that is greater than the data path reference voltage that is selected by a corresponding pass transistor. The control voltage is provided by a higher voltage power supply than the power supply that provides the data path reference voltage. In one embodiment, the higher voltage supply is a quiet supply that is not loaded with devices that switch during normal operation of the programmable switch such as CMOS devices. In another embodiment, the power supply that provides a voltage to an I/O circuit of the probable switch is the power supply that is utilized to provide the control voltage to the pass transistors. In a particular embodiment, the pass transistors comprise higher voltage tolerant devices than other devices in the programmable device. In a particular embodiment, the higher voltage supply is at least the data path reference voltage plus the threshold voltage of the pass transistors.
    Type: Grant
    Filed: December 18, 2000
    Date of Patent: November 26, 2002
    Assignee: Cypress Semiconductor Corp.
    Inventors: Greg J. Landry, Robert M. Reinschmidt, Timothy M. Lacey
  • Patent number: 6487677
    Abstract: Methods and associated systems using probabilistic methods for selecting among a plurality of diagnostic procedures to recover from an error condition in a managed device. Operation of a managed device is overseen by a management device. A management client process operable within the management device communicates with a management service operable within the managed device. Upon detection of an error condition within the managed device, the management service propagates an event to the management client so indicating an error condition. The management client in the management device responds to the event by requesting the managed device to determine the best options for recovery procedures. The managed device then computes a probability of success for each known recovery procedure based upon the present state of the managed device and based upon past successes or failures of recovery procedures for particular error conditions.
    Type: Grant
    Filed: September 30, 1999
    Date of Patent: November 26, 2002
    Assignee: LSI Logic Corporation
    Inventors: Ray M. Jantz, Matthew A. Markus
  • Patent number: 6487463
    Abstract: A system for actively cooling an electronic device is disclosed. The electronic device may be divided into a plurality of regions each containing one or more electrical or electronic components. A temperature sensor is positioned in each region to sense the temperature of the components contained in that region. Similarly, a temperature regulating device is positioned in each region. A controller monitors the temperature of each region as sensed by the temperature sensor and adjusts the amount of cooling provided to that region by the temperature regulating device, accordingly.
    Type: Grant
    Filed: June 8, 1998
    Date of Patent: November 26, 2002
    Assignee: Gateway, Inc.
    Inventor: George Thomas Stepp, III
  • Patent number: 6487692
    Abstract: A Reed-Solomon decoder capable of correcting two symbol errors in a codeword of a Reed-Solomon RS(128,122,7) code over a Galois field GF(128) is provided. In an exemplary embodiment, the Reed-Solomon decoder is suitable for use in cable modems with little or no loss in error performance over Reed-Solomon decoder correcting three errors in a codeword.
    Type: Grant
    Filed: December 21, 1999
    Date of Patent: November 26, 2002
    Assignee: LSI Logic Corporation
    Inventor: Robert Morelos-Zaragoza
  • Patent number: 6483354
    Abstract: Process voltage temperature compensation are used for a bus driver; specifically, a PCI-X 2.0 DDR Standard bus driver. Performance is improved by enhancing the speed of the PCI-X buffer by removing the statically controlled gate stages and providing for output signal slew control by dual use of on-resistance of signal pass transistors. Although directed to PCI-X technology, this circuitry may also be used in SCCI, controlled impedance drivers, and other buffers, where short propagation delay and signal integrity are of concern.
    Type: Grant
    Filed: August 24, 2001
    Date of Patent: November 19, 2002
    Assignee: LSI Logic Corporation
    Inventor: Frank Gasparik
  • Patent number: 6480105
    Abstract: A method for alerting a vehicle owner of recommended maintenance on the vehicle the initial step of entering vehicle identification data into a computer system. The computer system includes a database with vehicle maintenance data, a processor for processing the vehicle identification data and selecting appropriate vehicle maintenance data for the owner's vehicle, and a monitor for displaying the selected vehicle maintenance data. The computer will then alert the vehicle owner of specific service items needing attention from the selected vehicle maintenance data displayed. The step of alerting the vehicle owner includes visually alerting the owner with a flashing graphic display for particular service items needing attention.
    Type: Grant
    Filed: December 21, 2000
    Date of Patent: November 12, 2002
    Assignee: Auto Advisors, L.LC.
    Inventor: Brian S. Edwards
  • Patent number: 6480955
    Abstract: A system and method for managing device configuration changes. The system and method preferably comprises a management station which issues a configuration change request to a management device and waits for a reply from the managed device. The managed device receives the configuration change request from the management station and processes the change request until the configuration change request is durable on the managed device. The managed device then returns a status to the management station indicating that the configuration request is durable. The management station receives the status from the managed device and stops waiting for reply. In the meantime, the managed device continues processing the configuration change request.
    Type: Grant
    Filed: July 9, 1999
    Date of Patent: November 12, 2002
    Assignee: LSI Logic Corporation
    Inventors: Rodney A. DeKoning, Ray M. Jantz, William V. Courtright, II
  • Patent number: 6476737
    Abstract: The present invention describes a system and method for encoding a sequence of 64 bit digital data words into a sequence of 65 bit codewords having constraints of (d=0, G=11/I=10) for recording upon a magnetic medium within a magnetic recording channel are disclosed. The method for encoding a sequence of 64 bit digital data words into a sequence of codewords having 65 bits, comprising the steps of dividing each 64-bit digital data word into 8-bit bytes, encoding two 8-bit bytes to form a 17-bit word, forming five 11-bit intermediate blocks from the 8-bit bytes, encoding the five 11-bit intermediate blocks, and concatenating the five encoded 11-bit intermediate blocks and uncoded and unconstrained bits from the 64 bit digital data word to form a 65 bit codeword. A corresponding decoding method is also described. A byte shuffler may be used in the processing.
    Type: Grant
    Filed: November 16, 2001
    Date of Patent: November 5, 2002
    Assignee: LSI Logic Corporation
    Inventors: Joseph P. Caroselli, Shirish A. Altekar, Charles E. MacDonald
  • Patent number: 6471162
    Abstract: A railroad maintenance-of-way personnel warning system and method therefor provides advanced detecting and warning of oncoming trains encroaching the construction area. Magnetometer sensors detect an oncoming train whereby a warning signal is transmitted to a receiver unit at the construction zone. Warning alarms including a flashing light and siren horn are thereby activated to indicate the imminent danger whereupon the construction personnel may take cautionary and evasive action in sufficient time to avoid mishap.
    Type: Grant
    Filed: July 11, 2000
    Date of Patent: October 29, 2002
    Assignee: EVA Signal Corporation
    Inventor: Joseph A. Pace
  • Patent number: 6468048
    Abstract: A portable air compressor of the type having a horizontal compressed air storage tank is disclosed wherein the air compressor includes a stable base having a width at least substantially equal to the diameter of the compressed air storage tank. The air compressor may further include tie-down points for securing the air compressor to a platform.
    Type: Grant
    Filed: March 8, 2001
    Date of Patent: October 22, 2002
    Assignee: DeVilbiss Air Power Company
    Inventors: Robert F. Burkholder, Mark W. Wood, Crandall B. Barbour, Mike L. Davis, Fred M. Morgan, David W. Robenalt, Dave C. Smith
  • Patent number: 6442738
    Abstract: An RTL back annotator for applying back annotated data to the RTL code of an RTL simulation for verifying actual timing performance for an ASIC array after layout during RTL simulation parses through annotation data from the back annotation file for the ASIC layout and generates RTL delays for each wire and register in the ASIC layout. The RTL annotator then applies the generated RTL delays to the RTL compiled design, thereby emulating the delays that a gate level netlist would have. In this manner, an RTL simulation having timings of the real layout may be run.
    Type: Grant
    Filed: June 12, 2001
    Date of Patent: August 27, 2002
    Assignee: LSI Logic Corporation
    Inventor: Joseph J. Brehmer
  • Patent number: 6438046
    Abstract: A system and method for providing row redundancy for BISR of high density memory arrays without a timing penalty decreases capacitance of the memory array bitlines at least during accessing of rows of redundant memory of a memory array. In this manner, the amount of time required to access the redundant memory is limited so that no timing penalty is incurred by the memory.
    Type: Grant
    Filed: July 17, 2001
    Date of Patent: August 20, 2002
    Assignee: LSI Logic Corporation
    Inventor: Ghasi R. Agrawal
  • Patent number: 6431194
    Abstract: The present invention discloses an apparatus and method for protecting a condensate removal device from damage that may be caused when the condensate removal device comes into contact with foreign objects. The present invention discloses placing a shield around the condensate removal device to help prevent the condensate removal device from coming into contact with any foreign object. The present invention also discloses placing a removable cap around the condensate removal device and a condensate removal device that may recess within a mounting assembly.
    Type: Grant
    Filed: March 8, 2001
    Date of Patent: August 13, 2002
    Assignee: DeVilbiss Air Power Company
    Inventors: John W. Hardin, Mark W. Wood
  • Patent number: 6431844
    Abstract: A high pressure pump suitable for use in devices such as pressure washers or the like is disclosed wherein the pump's head assembly includes an integral start valve for allowing the fluid through the head assembly so the engine may be more easily started. When the pump reaches a predetermined rate of flow of the fluid, the start valve assembly closes to circulate the fluid through said pump assembly.
    Type: Grant
    Filed: August 14, 2000
    Date of Patent: August 13, 2002
    Assignee: DeVilbiss Air Power Company
    Inventors: Shane Dexter, Allen Palmer, Mark Wood
  • Patent number: 6433598
    Abstract: A clock tree deskew circuit dynamically minimizes skew in clock signals that synchronize operation of synchronized circuit components of an integrated circuit. The clock tree deskew circuit reduces the clock tree skew in repeated intervals over a period of time. The clock tree deskew circuit is then turned off to prevent unnecessary further adjustments to the clock signals, but can be turned back on when conditions change that alter the clock tree skew. The clock signals are paired together in a continuous loop such that each clock signal is the first clock signal of the pair when paired with the next clock signal and is the second clock signal when paired with the one before it. The clock tree deskew circuit detects the absolute skew between each pair of the clock signals. The clock tree deskew circuit adjusts the first clock signal of each pair toward the second clock signal of the pair to reduce the skew between the two clock signals.
    Type: Grant
    Filed: July 25, 2001
    Date of Patent: August 13, 2002
    Assignee: LSI Logic Corporation
    Inventor: Richard T. Schultz
  • Patent number: 6434657
    Abstract: A method and apparatus for accommodating irregular memory write word widths allow for writing to multiple rows in a memory so as to reduce or eliminate holes in the address read space. First and second memory blocks are provided that include a first bitcell selectable by a first write bitline and a second bitcell selectable by a second write bitline. Where a write word width is not equal to a read word width and is not some factor of a power of two times the read word width, the column decode to read out the entire word is not a power of two, and holes in the read address space will exist. When the write address is even, a first range of bits is written to the first block on a first write bitline, a second range of bits is written to the second block on the first write bitline, and a third range of bits is written to the first block on a second write bitline.
    Type: Grant
    Filed: September 20, 2000
    Date of Patent: August 13, 2002
    Assignee: LSI Logic Corporation
    Inventor: Jeff S. Brown
  • Patent number: 6429714
    Abstract: A multilevel clock tree uses a temporary clock buffer or reference signal in a clock tree deskew circuit to dynamically minimize skew in a variable delay clock signal that synchronizes operation of synchronized circuit components of an integrated circuit. There are multiple temporary clock buffer signals at each level of the multilevel clock tree. Skew between the temporary clock buffer signals are minimized by providing identical path lengths and path geometries at each level of the temporary clock buffer. The clock tree deskew circuit reduces the clock tree skew, on a level by level basis, in repeated intervals over a period of time. When each level of the tree deskew circuit is deskewed, that level of the clock tree deskew circuit is then turned off to prevent unnecessary further adjustments to the clock signals, but can be turned back on when conditions change that alter the clock tree skew.
    Type: Grant
    Filed: March 29, 2002
    Date of Patent: August 6, 2002
    Assignee: LSI Logic Corporation
    Inventor: Richard T. Schultz
  • Patent number: D464548
    Type: Grant
    Filed: October 3, 2001
    Date of Patent: October 22, 2002
    Assignee: DeVilbiss Air Power Company
    Inventor: Fred M. Morgan
  • Patent number: D464857
    Type: Grant
    Filed: October 3, 2001
    Date of Patent: October 29, 2002
    Assignee: DeVilbiss Air Power Company
    Inventor: Fred M. Morgan
  • Patent number: D465141
    Type: Grant
    Filed: November 8, 2001
    Date of Patent: November 5, 2002
    Assignee: DeVilbiss Air Power Company
    Inventor: Fred M. Morgan