Abstract: A semiconductor memory device allows a read command to be inputted thereto after a passage of a relatively short time period from a point in time where a write command has been inputted thereto. A method of operating the semiconductor memory device includes inputting a write command, inputting a read command in a preset period of time after the write command has been inputted, loading read data of a memory cell onto a data bus in response to the read command; and loading write data from outside of the semiconductor memory device onto the data bus in response to the write command.

Abstract: Devices and methods store provisioning data for use in one or mobile devices within a SIM card enclosed within a personal article, such as a wrist watch or item of jewelry. A close range communication link, such as a near field communication (NFC) protocol link, is used to transmit the provisioning data from the personal article to one or more mobile devices. The close range communication link may also be used to transmit updated provisioning data received by a mobile device in an over the air updating procedure via a cellular communications network link to the personal item for storage in the SIM card housed within a personal article. The mobile device may authenticate itself to the personal article prior to the transmission of provisioning data between the devices.

Abstract: An electrostatic discharge protection device includes a substrate where an active region is defined by an isolation layer, a gate electrode simultaneously crossing both the isolation layer and the active region, and a junction region formed in the active region at both sides of the gate electrode and separated from the isolation layer by a certain distance in a direction where the gate electrode is extended. The electrostatic discharge protection device is able to prevent the increase of a leakage current while securing an electrostatic discharge protection property that a semiconductor device requires.

Abstract: An insert is provided in a flow path adjacent to the input and/or output port of a plate heat exchanger to shield heat transfer elements adjacent to the port from high velocity flow. By deflecting and redirecting the high velocity flow from the port, vibration induced stress to the heat transfer elements can be minimized. The insert is provided with a converging nozzle that directs the flow into a narrowed body. The outlet of the insert can be formed as an open end of the body or as a contoured opening in the side wall of the body. Flow can also be more uniformly distributed to the flow channels defined between the heat transfer elements.

Abstract: Embodiments of the invention provide for shielding a sensitive file on a computer that can connect to a server computer via a network. The computer may determine whether it complies with security compliance requirements sent from another computer or not in response to a read instruction or a write instruction of the sensitive file by application software, and encrypt the sensitive file with an encryption key.

Abstract: A phase locked loop includes a phase lock unit configured to compare a phase of a reference clock with a phase of a feedback clock and to generate an internal clock based on the comparison; a delay lock unit configured to compare the reference clock with the internal clock, and to generate the feedback clock which is delayed in response to a control voltage based on the comparison; and a start voltage enable unit configured to receive an enable signal and to apply a start voltage as the control voltage in response to the enable signal.

Abstract: A computer-implemented method for managing price information. Embodiments include receiving a mapping of interconnected components, identifying as a first subset components subject to a first fixed price agreement not subject to a second fixed price agreement that overlaps the first fixed price agreement, identifying as a second subset the components subject to the second fixed price agreement not subject to the first fixed price agreement, and identifying as a third subset the components subject to both the first fixed price agreement and the second fixed price agreement. The method also includes receiving a price change for a price associated with a component in one of the subsets of components, and distributing an offset of the price change to components in the other subsets of components.

Abstract: An implant delivery catheter enables permanent modification of the implant length in the vicinity of the treatment site prior to radial expansion thereof. The implant is releasable carried between inner and outer tubular members of the delivery catheter which, upon repositioning relative to one another using an actuator mechanism, impart any of tensile, compressile or torquing forces to the implant causing permanent modification of the implant length. In one embodiment, the circumference of the implant is substantially similar both before and after modification of the implant length. In another embodiment, the implant includes a plurality of strut sections interconnected by bridges which are capable of the deformation along the longitudinal axis of the implant.

Abstract: A WCDMA enabled user equipment device configured to have functions collectively or selectively idle to conserve power. A discontinuous receiver is used to detect and read network messages and report the messages to the computer within the WCDMA enabled user equipment device. The computer then activates functions previously powered down to receive incoming messages for the user of the device. The discontinuous receiver is also used when the device is active to read network messages, freeing a modem of the device to operate on user messaging; and therefore, enhancing user related performance.

Abstract: In an erase method of a flash device, including a page buffer configured to transfer a virtual voltage in response to a discharge signal and further comprising strings each including memory cells and coupled to the page buffer via a respective bit line, applying a ground voltage to a gate of each of the memory cells and erasing the memory cells coupled to a selected bit line by supplying the virtual voltage wherein the virtual voltage is applied to the selected bit line and a unselected bit line.

Abstract: A delay locked loop includes a replica delay oscillator unit, a division unit, a pulse generation unit, a code value output unit, and a delay line. The replica delay oscillator unit generates a replica oscillation signal having a period corresponding to a replica delay. The division unit receives the replica oscillation signal and a clock signal and divides the replica oscillation signal and the clock signal at a first or second ratio in response to a delay locking detection signal. The pulse generation unit generates a delay pulse having a pulse width corresponding to a delay amount for causing a delay locking. The code value output unit adjusts a code value corresponding to the pulse width of the delay pulse in response to the delay locking detection signal. The delay line delays the clock signal in response to the code value.

Abstract: A semiconductor memory device includes: a first bank and a second bank; one or more first data input/output pads disposed at one side of the first bank and used in access to data of the first bank; one or more second data input/output pads disposed at one side of the second bank and used in access to data of the second bank; a first cyclic redundancy code (CRC) generation circuit for generating a first CRC using a plurality of data output from the first bank and outputting the generated first CRC through the first data input/output pads; and a second CRC generation circuit for generating a second CRC using a plurality of data output from the second bank and outputting the generated second CRC through the second data input/output pads.

Abstract: A technique for sequencing nucleic acids in an automated or semi-automated manner is disclosed. Sample arrays of a multitude of nucleic acid sites are processed in multiple cycles to add nucleotides to the material to be sequenced, detect the nucleotides added to sites, and to de-block the added nucleotides of blocking agents and tags used to identify the last added nucleotide. Multiple parameters of the system are monitored to enable diagnosis and correction of problems as they occur during sequencing of the samples. Quality control routines are run during sequencing to determine quality of samples, and quality of the data collected.

Abstract: The present invention relates to a liquid acidic hard surface cleaning composition having a pH of from 2 to 2.9 and comprising formic acid and an alkaline material.

Abstract: An elastomeric nanocomposite is produced from an isobutylene-based polymer and a layered nanofiller. The process of preparing the nanocomposite includes the steps of a) polymerizing isobutylene monomers and multiolefin monomers to produce an isobutylene-based polymer; b) completing at least one mass transfer dependent stage in the process wherein, after completion of the stage and prior to any recovery of the polymer, the polymer is dissolved in a solvent to create a polymer cement; c) contacting the layered nanofiller and the polymer solvent to obtain the nanocomposite; and d) recovering the nanocomposite. The layered nanofiller may be in a slurry prior to contacting with the polymer cement.

Abstract: A method for forming a fine pattern in a semiconductor device using a quadruple patterning includes forming a first partition layer over a first material layer which is formed over a substrate, performing a photo etch process on the first partition layer to form a first partition pattern, performing an oxidation process to form a first spacer sacrificial layer over a surface of the first partition pattern, forming a second spacer sacrificial layer over the substrate structure, forming a second partition layer filling gaps between the first partition pattern, removing the second spacer sacrificial layer, performing an oxidation process to form a third spacer sacrificial layer over a surface of the second partition layer and define a second partition pattern, forming a third partition pattern filling gaps between the first partition pattern and the second partition pattern, and removing the first and third spacer sacrificial layers.

Abstract: A semiconductor integrated circuit includes a first ground voltage pad, a second ground voltage pad, an internal voltage generation unit, and a division unit. The first ground voltage pad is configured to receive a first ground voltage. The second ground voltage pad is configured to receive a second ground voltage. The internal voltage generation unit includes a comparison unit configured to compare a reference voltage with a feedback voltage by using the first ground voltage, and a driving unit configured to drive an internal voltage terminal in response to an output signal of the comparison unit. The division unit is coupled between the internal voltage terminal and the second ground voltage pad, and configured to divide a voltage of the internal voltage pad and generate the feedback voltage supplied to the internal voltage generation unit.

Abstract: A semiconductor integrated circuit includes a semiconductor chip. The semiconductor chip includes a well arranged to receive a first well bias voltage from a well biasing region, a through-chip-via arranged to penetrate the well, and a guard region disposed around the through-chip-via with space in-between and arranged to apply a second well bias voltage to the well.

Abstract: A method for forming an isolation layer of a semiconductor device includes forming a trench in a substrate, forming a high-density plasma (HDP) oxide layer filling a portion of the trench, forming a spin-on-dielectric (SOD) oxide layer having a certain height over the HDP oxide layer, performing a thermal treatment, and forming an enhanced high-aspect-ratio process (eHARP) oxide layer filling another portion of the trench over the SOD oxide layer.