Abstract: A semiconductor memory device is able to generate an output enable signal in response to a read command and CAS latency information. The semiconductor memory device includes a delay locked loop configured to detect a phase difference of an external clock signal and a feedback clock signal, generate a delay control signal corresponding to the detected phase difference, and generate a DLL clock signal by delaying the external clock signal for a time corresponding to the delay control signal, a delay configured to output an active signal as an output enable reset signal in response to the delay control signal and an output enable signal generator configured to be reset in response to the output enable reset signal and generate an output enable signal in response to a read signal and a CAS latency signal by counting the external clock signal and the DLL clock signal.

Abstract: A pulse control device is maintained with a constant pulse width corresponding to a change of process or temperature. The pulse control device comprises a fuse set for selectively outputting a delay increase signal and a delay decrease signal that have a different state based on a cutting or non-cutting state of a fuse on which information on a change of process is programmed, and a pulse generator provided with a plurality of delay cells with predetermined time delay for selectively increasing or decreasing the number of the plurality of delay cells depending on the delay increase signal and the delay decrease signal to generate an internal clock with a pulse width corresponding to the number of the increased or decreased delay cells.

Abstract: An internal supply voltage generating circuit includes a clock comparator configured to compare a first clock signal having clock information corresponding to a level of a reference voltage with a second clock signal having clock information corresponding to a level of an internal supply voltage, a control signal generator configured to generate a driving control voltage having a voltage level corresponding to an output signal of the clock comparator; and a driver configured to drive a terminal of the internal supply voltage in response to the driving control voltage.

Abstract: A torque nut assembly includes a multiple-piece nut body and a ring-shaped compression assembly. The compression assembly circumferentially engages the nut body to capture its multiple pieces therein. The compression assembly can position the nut body to define a threaded axial passage or to allow radial expansion of the multiple pieces such that the threaded axial passage is segmented in correspondence with the nut body's multiple pieces. At least one structure is provided to lock the compression assembly when the threaded axial passage is defined.

Abstract: A computer-implemented method of incorporating a module within a circuit design can include, responsive to identifying the module to be imported into the circuit design, automatically identifying each port of the module, displaying a list of the ports of the module, and receiving a user input selecting a plurality of ports of the module for inclusion in an interface through which the module communicates with the circuit design. Responsive to a user input specifying an interface type, the interface type can be associated with the plurality of ports. The interface type can be associated with a port list including standardized ports. Individual ones of the plurality of ports can be automatically matched with standardized ports from the port list. A programmatic interface description specifying the interface for the module can be output.

Abstract: A code address memory (CAM) cell memory device comprises a first storage unit comprising a first nonvolatile memory cell configured to output a power source voltage in response to a read voltage, and a second storage unit comprising a second nonvolatile memory cell configured to output a ground voltage in response to the read voltage.

Abstract: A fuse structure for a semiconductor integrated circuit (IC) can include a first node comprising a region of a metal layer of an IC manufacturing process and a second node comprising a region of a conductive layer residing on a layer of the IC manufacturing process below the metal layer of the first node. The fuse structure can include a fuse link comprising a conductive material, positioned substantially perpendicular to each of the metal and conductive layers. An upper end of the fuse link couples to the first node and a lower end of the fuse link, that is distal to the upper end, couples to the second node.

Abstract: A flash memory device includes an isolation layer formed on an isolation region of a semiconductor substrate, a tunnel insulating layer formed on an active region of the semiconductor substrate, a first conductive layer formed over the tunnel insulating layer, a dielectric layer formed on the first conductive layer and the isolation layer, a first trench penetrating the dielectric layer on the isolation layer to separate parts of the dielectric layer, a second trench formed on the isolation layer and expanded from the first trench, and a second conductive layer formed over the dielectric layer to fill the first and second trenches.

Abstract: An apparatus, system, and method to generate a graphical representation of a social network. The computer program product includes a computer useable storage medium to store a computer readable program that, when executed on a computer, causes the computer to perform operations related to generating a graphical representation of a social network. The operations include an operation to display a first node and a second node in a social network. The operations also include an operation to display an actual quality indicator representative of an actual level of quality of a connection between the first and second nodes of the social network. The operations also include an operation to display a target quality indicator representative of a target level of quality of the connection between the first and second nodes of the social network.

Abstract: A computer-implemented method for determining, from a system including a plurality of data center resources, at least one configuration of data center resources for an implementation of an application. The method includes receiving application information and receiving information regarding known internal features up the data center resources. The method also includes provisioning the system of data center resources and creating possible configurations of data center resources for implementing application. The method also includes correlating models and data center resources to create an interrelated representation of the models and the data center resources. The models predict a relationship of parameters for the possible configurations.

Abstract: An integrated circuit includes a CML swing reference voltage generating unit, a CML bias control voltage generating unit and a CML buffering unit. The CML swing reference voltage generating unit determines a level of a CML swing reference voltage in response to a frequency setting code and a CML bias control voltage. The CML bias control voltage generating unit compares the level of the CML swing reference voltage with a level of a CML target reference voltage and determines a level of the CML bias control voltage based on the comparison result. The CML buffering unit generates a CML output signal swinging in a CML region by buffering an input signal and determines a swing level of the CML output signal on the basis of the level of the CML swing reference voltage in response to the frequency setting code and the CML bias control voltage.

Abstract: This invention relates to compounds of the formula (I): or pharmaceutically acceptable salts thereof, wherein: A, B, R1, R2 and R3 are each as described herein, and compositions containing such compounds and the use of such compounds in the treatment of a condition mediated by CB2 receptor binding activity such as, but not limited to, inflammatory pain, nociceptive pain, neuropathic pain, fibromyalgia, chronic low back pain, visceral pain, acute cerebral ischemia, pain, chronic pain, acute pain, post herpetic neuralgia, neuropathies, neuralgia, diabetic neuropathy, HIV-related neuropathy, nerve injury, rheumatoid arthritic pain, osteoarthritic pain, back pain, cancer pain, dental pain, fibromyalgia, neuritis, sciatica, inflammation, neurodegenerative disease, cough, broncho constriction, irritable bowel syndrome (IBS), inflammatory bowel disease (IBD), colitis, cerebrovascular ischemia, emesis such as cancer chemotherapy-induced emesis, rheumatoid arthritis, asthma, Crohn's disease, ulcerative colitis, asthma

Abstract: One embodiment of the present invention provides a method for incrementally maintaining a Bernoulli sample S with sampling rate q over a multiset R in the presence of update, delete, and insert transactions. The method includes processing items inserted into R using Bernoulli sampling and augmenting S with tracking counters during this processing. Items deleted from R are processed by using the tracking counters and by removing newly deleted items from S using a calculated probability while maintaining a degree of uniformity in S.

Abstract: Cell timing is detected by first trying to detect a target handover cell through detecting a primary synchronization channel (P-SCH) followed by a common pilot channel (CPICH). If that fails, N number of retrials is performed using a full-window search on the CPICH. The full-window CPICH search is performed blindly, without any slot timing information from the P-SCH. Performance is improved while maintaining the benefits of faster acquisition methods in good channel conditions. The full-window search is more time consuming, but takes advantage of the stronger CPICH transmission. In good channel conditions, a mobile device can proceed quickly with the normal method of timing acquisition. With failure, the mobile device can switch to the longer search which has a higher probability of successfully completing the hard handover procedure. The overall effect is a higher success rate of hard handovers without a uniform increase of time spent in cell timing acquisition.

Abstract: Methods and systems for auto-generating threads on web forums are described. Comments are received on web content contained on a web page within a web site, where the web site further includes a web forum. The comments can be monitored to determine if a comment threshold is reached, and a web content thread can be auto-generated in the web forum when the comment threshold is reached.

Abstract: A nonvolatile memory device includes a data sense amplifier configured to supply a data detection current to a memory cell and detect a data detection voltage having a voltage level corresponding to a resistance of the memory cell, a first switching element configured to selectively transfer the data detection current to the memory cell, and a second switching element configured to be turned on simultaneously with the first switching element to selectively transfer the data detection current to the memory cell. The first switching element and the second switching element have a complementary voltage transfer characteristic.