Patents Represented by Attorney T

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  • Semiconductor memory device and method for generating internal control signal
    Patent number: 8127169
    Abstract: A semiconductor memory device includes: a command input unit configured to receive a plurality of external commands in synchronization with a rising edge of an internal clock to generate a plurality of pre-control signals; an output control signal generating unit configured to receive the plurality of external commands to generate an output control signal in synchronization with a falling edge of the internal clock prior to the rising edge of the internal clock; an address input unit configured to receive a plurality of addresses to output a plurality of internal addresses in response to the output control signal; and an internal driving signal generating unit configured to receive the plurality of internal addresses and the plurality of pre-control signals to generate a plurality of internal driving control signals.
    Type: Grant
    Filed: December 7, 2007
    Date of Patent: February 28, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Keun-Kook Kim
  • Production of activated char using hot gas
    Patent number: 8124561
    Abstract: A gas mixture preheated to high temperatures using an oxy-fuel, an oxygen-enriched air-fuel or an air-fuel burner is used to devolatilize and partially oxidize carbonaceous feedstock, thereby producing an active residual char that can be used in applications utilizing activated carbon. Use of hot gas and ground carbonaceous feedstock allows the equipment to be minimized, thereby allowing the activated carbon to be produced at or near points of use, for example the production of activated char at or near utility boilers for use in the reduction of mercury emissions from flue gas streams.
    Type: Grant
    Filed: March 26, 2010
    Date of Patent: February 28, 2012
    Assignee: Praxair Technology, Inc.
    Inventors: Lawrence E. Bool, III, Chien-Chung Chao, Mark K. Weise, Jurron L. D. Bradley
  • Methods for singulating abutting articles
    Patent number: 8123021
    Abstract: Methods for singulating laterally abutting conveyed articles in a conveyor (60). The method includes separating laterally abutting articles by means of a first conveyor section (62) having in-line rollers (64) or oblique rollers rotating at a first speed in a conveying direction (70) and a second laterally adjacent conveyor section (63) having oblique rollers (65) rotating at a second speed in a direction causing articles atop the oblique rollers (65) in the second section (63) to diverge from articles atop the rollers in the first section. Differing the roller speeds helps the abutting articles to increase their separation in the conveying direction.
    Type: Grant
    Filed: August 27, 2007
    Date of Patent: February 28, 2012
    Assignee: Laitram, L.L.C.
    Inventors: Joseph M. DePaso, Felix H. Lapeyre, III
  • Apparatus for generating output data strobe signal
    Patent number: 8125841
    Abstract: An apparatus for generating an output data strobe signal include a timing control unit configured to detect a specific data pattern and to generate a plurality of timing control signals corresponding to the detected data pattern in response to a clock signal; and a strobe signal generating unit configured to generate at least one strobe signal in response to the clock signal, and to adjust transition timings of the strobe signal in response to the timing control signals.
    Type: Grant
    Filed: December 30, 2009
    Date of Patent: February 28, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Seong-Hwi Song
  • Bingo game
    Patent number: 8123607
    Abstract: A method and gaming device for wagering on and playing a bingo-type game is disclosed. More particularly, a method allows a player to use strategy to select or daub a number of bingo balls in a bingo-type game and forgo daubing other balls, thereby adding a new level of player interaction, and skill to the game of bingo while maintaining other features of a bingo game such as playing until at least one player wins the game.
    Type: Grant
    Filed: October 24, 2005
    Date of Patent: February 28, 2012
    Inventor: Shawn Michael Van Asdale
  • Semiconductor memory device for low voltage
    Patent number: 8125844
    Abstract: A semiconductor memory device includes a first cell array including a plurality of unit cells and a bit line sense amplifying unit for sensing and amplifying data signals stored in the unit cells. Each unit cell is provided with a PMOS transistor and a capacitor. Therefore, the semiconductor memory device efficiently operates with low voltage without any degradation of operation speed.
    Type: Grant
    Filed: October 13, 2009
    Date of Patent: February 28, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventors: Hee-Bok Kang, Jin-Hong Ahn, Sang-Don Lee
  • Semiconductor device with buried gate and method for fabricating the same
    Patent number: 8120099
    Abstract: A semiconductor device and method for fabricating the same is provided. The semiconductor device includes a trench formed in a substrate, a junction region formed in the substrate on both sides of the trench, a first gate insulation layer formed on the surface of the trench, a first buried conductive layer formed over the first gate insulation layer to fill a portion of the trench, a second buried conductive layer formed between the first buried conductive layer and the first gate insulation layer to provide a gap between the first buried conductive layer and the first gate insulation layer, and a second gate insulation layer buried in the gap.
    Type: Grant
    Filed: November 11, 2009
    Date of Patent: February 21, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventors: Dae-Young Seo, Doo-Kang Kim
  • Method for fabricating semiconductor device using dual damascene process
    Patent number: 8119523
    Abstract: A method for fabricating a semiconductor device using a dual damascene process is provided. The method includes forming a dielectric layer over a conductive layer, forming a via hole exposing the conducting layer by selectively etching the dielectric layer, projecting a portion of the dielectric layer at an edge of the via hole by selectively etching the dielectric layer to a first depth, and forming a trench by selectively etching the dielectric layer to a second depth, wherein the trench is overlapped with the via hole to form a dual damascene pattern.
    Type: Grant
    Filed: April 30, 2009
    Date of Patent: February 21, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jin-Ho Yang
  • Impedance adjusting device
    Patent number: 8120381
    Abstract: An impedance adjusting device includes a calibration unit configured to generate an impedance code for adjusting a termination impedance value, a plurality of termination units configured to be enabled by resistance selection information and terminate an interface node in response to the impedance code, a resistance providing unit coupled in parallel to the plurality of termination units and configured to provide a resistance in response to the resistance selection information, and a selection signal generation unit configured to generate the resistance selection information according to a target impedance value.
    Type: Grant
    Filed: July 9, 2010
    Date of Patent: February 21, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Hyeong-Jun Ko
  • Pole bridge for a battery
    Patent number: 8119282
    Abstract: The invention relates to a cell connector (6) for a battery, especially for absorbing, in conjunction with at least one damping element (9), the vertical forces that are caused by the impact of shocks. The cell connector (6), at one end, is connected to the positive or negative electrodes (4, 5) which are received in a housing (2) having a housing cover (3), and, at the other end, comprises at least one terminal (7, 8) projecting from the housing cover (3). The aim of the invention is to elastically dampen the electrode plates (4, 5) of an accumulator (1) which are disposed inside a housing (2). For this purpose, a terminal (6) having a supporting shoulder (11), integrally molded thereto, is used in the housing (2), a damping element (9), disposed between the housing cover (3) of an accumulator (1) and the cell connector (6), coming to rest thereon.
    Type: Grant
    Filed: June 8, 2006
    Date of Patent: February 21, 2012
    Assignee: Exide Technologies GmbH
    Inventors: Nils Hansson, Detlef Rathmann, Bjørn Haraldsen
  • Water filter materials and water filters containing a mixture of microporous and mesoporous carbon particles
    Patent number: 8119012
    Abstract: A filter and filter material for providing or treating potable water is provided. The filter includes a housing having an inlet and an outlet, a filter material disposed within the housing, the filter material formed at least in part from a mixture of a plurality of mesoporous and microporous activated carbon particles. Preferably, at least some of the mesoporous activated carbon filter particles are coated with a cationic polymer, and even more preferably, at least some of the particles are coated with a cationic polymer and silver or a silver containing material. Kits comprising filters and information relating to the reduction, killing or removal of bacteria, viruses, microbials, and TTHM are also provided.
    Type: Grant
    Filed: March 7, 2011
    Date of Patent: February 21, 2012
    Assignee: The Procter & Gamble Company
    Inventors: Jeannine Rebecca Bahm, Andrew Thomas Pearks, Guillermo Matias Vidal, Dimitris Ioannis Collias, Michael Donovan Mitchell, Robert E. Astle, Katharine L. K. Faye, Robert Andrew Governal, Thomas J. Hamlin, Rebecca A. Lucht, Hemang Patel
  • Semiconductor device including ruthenium electrode and method for fabricating the same
    Patent number: 8120180
    Abstract: A semiconductor device includes a semiconductor substrate, an insulation pattern on the semiconductor substrate, and an etch stop layer on the insulating pattern, the insulation pattern and the etch stop layer defining a contact hole that exposes the substrate, a first plug filled in a portion of the contact hole, a diffusion barrier layer formed above the first plug and in a bottom portion and on sidewalls of a remaining portion of the contact hole, a second plug fainted on the diffusion barrier layer and filled in the contact hole, and a storage node coupled to and formed on the second plug.
    Type: Grant
    Filed: July 16, 2010
    Date of Patent: February 21, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventors: Jin-Hyock Kim, Jae-Sung Roh, Seung-Jin Yeom, Kee-Jeung Lee, Han-Sang Song, Deok-Sin Kil, Young-Dae Kim
  • Test method for nonvolatile memory device
    Patent number: 8120977
    Abstract: A test method for nonvolatile memory devices where, in one aspect of the method, a specific operation mode is selected according to a signal input through a single I/O pin in a period in which a write enable signal is inactivated. The write enable signal or a read enable signal is activated according to the selected operation mode. A plurality of signals is input through the single I/O pin in a period in which the write enable signal is activated. The plurality of signals is output through the single I/O pin in a period in which the read enable signal is activated.
    Type: Grant
    Filed: January 29, 2009
    Date of Patent: February 21, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventors: Wan Seob Lee, Jin Yong Seong
  • Semiconductor memory apparatus and test circuit therefor
    Patent number: 8120972
    Abstract: A test circuit for a semiconductor memory apparatus of an open bit-line structure includes a compression part configured to, in response to test data read from a plurality of memory cells included in a test target cell mat and a compression control signal generated from a compression control signal generating part, compress the test data that are read from the memory cells that share a sense amplifier block and sequentially output compression test signals.
    Type: Grant
    Filed: April 28, 2009
    Date of Patent: February 21, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Seung Bong Kim
  • Semiconductor device
    Patent number: 8120442
    Abstract: A semiconductor device includes transmission lines for conveying signals and transition detectors, each of which checks whether a transmission signal on each of the plurality of transmission lines is transited. If the signal is transited, its transition shape is detected. A signal mode determining unit determines signal transmission modes between adjacent transmission lines in response to output signals from the plurality of transition detectors. Delay units are coupled to the respective transmission lines for adjusting transmission delays of the transmission signals depending on corresponding output signal from the signal mode determining units.
    Type: Grant
    Filed: November 7, 2008
    Date of Patent: February 21, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventors: Ji-Wang Lee, Kun-Woo Park, Yong-Ju Kim, Hee-Woong Song, Ic-Su Oh, Hyung-Soo Kim, Tae-Jin Hwang, Hae-Rang Choi
  • Two-tier streamer communication system
    Patent number: 8120507
    Abstract: A two-tier communication system for a seismic streamer. The communication system operates over an unshielded twisted-pair communication line extending the length of the streamer. Repeater units having a repeater function and a device controller function divide the twisted pair into line segments. Coils on each segment couple signals inductively to collocated external devices in a low-speed 2400 baud FSK data link between the devices and an associated device controller. A Gaussian 8-level FSK high-speed 60 kbit/s data link is established along all the segments with the repeaters re-transmitting boosted signals along the entire length of the communication line. The coils are transparent at the high-speed data rate. Time division multiple access (TDMA) or frequency division multiple access (FDMA) is used to accommodate the two links on the single twisted pair.
    Type: Grant
    Filed: March 25, 2009
    Date of Patent: February 21, 2012
    Assignee: Ion Geophysical Corporation
    Inventors: Robert E. Rouquette, Clem B. Guillot, III, Robert H. Kemp, Jr., Dale J. Lambert, Daniel B. Seale
  • Congestion elimination using adaptive cost schedule to route signals within an integrated circuit
    Patent number: 8122420
    Abstract: A computer-implemented method of routing a circuit design for a target integrated circuit (IC) can include determining a characterization of routing congestion of the circuit design within the target IC and determining a first order cost component of using routing resources of the target IC according to the characterization. The method can include determining a higher order cost component of using routing resources of the target IC according to the characterization and assigning signals of the circuit design to routing resources according to costs calculated using the first order cost component and the higher order cost component. Signal assignments of the circuit design can be output.
    Type: Grant
    Filed: June 22, 2009
    Date of Patent: February 21, 2012
    Assignee: Xilinx, Inc.
    Inventors: Parivallal Kannan, Sanjeev Kwatra
  • Package with surface ornamentation
    Patent number: D654367
    Type: Grant
    Filed: August 2, 2010
    Date of Patent: February 21, 2012
    Assignee: PUR Water Purification Products, Inc.
    Inventors: Clancy Gerald Boyer, Frank Delmar Macaulay
  • Package with surface ornamentation
    Patent number: D654368
    Type: Grant
    Filed: August 2, 2010
    Date of Patent: February 21, 2012
    Assignee: PUR Water Purification Products, Inc.
    Inventors: Clancy Gerald Boyer, Frank Delmar MacAulay
  • Package with surface ornamentation
    Patent number: D654804
    Type: Grant
    Filed: August 2, 2010
    Date of Patent: February 28, 2012
    Assignee: The Procter & Gamble Company
    Inventors: Clancy Gerald Boyer, Frank Delmar Macaulay