Abstract: An apparatus and method for the dynamic detection and compensation of performance variations within an integrated circuit (IC) is provided to detect performance variations within the IC at any stage of test or operation. An arbitrary reference signal is utilized in conjunction with an internal oscillation device to establish a speed reference that may be used to characterize the IC. Dynamic detection and compensation may also be configured within a plurality of geographic locations within the IC, so that performance variations may be detected and compensated. Test data that is indicative of the IC's performance may be dynamically generated continuously, or at programmable intervals, so that performance variations caused by virtually any source may be substantially detected and compensated at any point in time of the IC's life cycle.

Abstract: A phase change memory device includes a signal generator configured to generate first and second sensing and amplifying enable signals which are sequentially activated during an activation period of a word line selection signal and each of which has a certain activation period length, a resistance sensor configured to sense a resistance value by applying a certain operation current to a phase change memory cell corresponding to the word line selection signal during an activation period of the first sensing and amplifying enable signal and a voltage level amplifier configured to logically determine a voltage level of the resistance sensing signal based on a voltage level of a logic reference signal during an activation period of the second sensing.

Abstract: A delay locked loop includes: a control voltage generator configured to generate a voltage control signal having a voltage level corresponding to a phase difference between an external clock and a feedback clock; a voltage controlled delay line configured to generate a plurality of output signals by reflecting a different delay time on the external clock in response to the voltage control signal; an internal clock multiplexer configured to output one of the plurality of output signals as an internal clock in response to a skew information signal; a delay replica model configured to output the feedback clock by reflecting a delay of an actual clock/data path on the internal clock; and a skew information signal generator configured to generate the skew information signal.

Abstract: A nonvolatile ferroelectric memory device includes a plurality of unit cells. Each of the unit cells includes a cell capacitor and a cell transistor. The cell capacitor includes a storage node, a ferroelectric layer, and a plate line. The cell capacitors of more than one of the plurality of unit cells are provided in a trench.

Abstract: Disclosed herein is a method for global motion estimation for video stabilization. The method enables selecting a video frame from a video stream. The method further enables downscaling the video frames by factor close to 2 in a two dimensional range, dividing the downscaled video frame into a plurality of macroblocks, performing motion estimation for the macroblocks to generate a set of local motion vectors. Further, the method enables selecting macroblocks representing global motion vectors from the set of local motion vectors, computing a single global motion vector for the selected macroblocks and determining occurrence of at least one of: scene change, illumination change or crossing object and modifying the single global vector to compensate for errors induced due to occurrence of at least one of: scene change, illumination change or crossing object.

Abstract: A semiconductor memory device, having a 6F2 open bit line structure, connects each bit line of a bit line pair to a respective bit line of a neighboring bit line pair for a precharge operation so that a layout size of the semiconductor memory device decreases. Plural first precharge units each precharge one bit line of a first bit line pair and one bit line of a second bit line pair in response to a bit line equalizing signal. Plural sense amplifiers each sense a data bit supplied to a respective one of the first and second bit line pairs and amplify sensed data.

Abstract: A method of programming a nonvolatile memory device includes performing a first LSB program operation on memory cells coupled to a selected word line in order to store least significant bit (LSB) data in the memory cells, performing a first most significant bit (MSB) program operation on the memory cells coupled to the selected word line, such that threshold voltages of the memory cells rise up to a temporary target voltage less than a target voltage, performing a second most significant bit (MSB) program operation on memory cells coupled to a neighboring word line neighboring the selected word line in order to store most significant bit (MSB) data in the corresponding memory cells, and performing a third most significant bit (MSB) program operation, after performing the second most significant bit (MSB) program operation, on the memory cells on which the first most significant bit (MSB) program operation has been performed, such that the threshold voltages of the memory cells coupled to the selected word lin