Abstract: The present invention relates to a master transceiver circuit meant to be coupled by a telephone line to a slave transceiver circuit, the master circuit including a digital phase-locked loop for reconstructing a clock from an incoming bit flow, the phase difference between the reconstructed clock and an internal clock corresponding to the content of a phase counter of the phase-locked loop. The circuit includes a bit counter clocked by the internal clock, initialized upon transmission of a predetermined signal, and stopped upon detection of the return of the predetermined signal transmitted back by the slave transceiver circuit; and means for calculating the delay introduced by the telephone line based on the contents of the phase and bit counters.

Abstract: Two different types of memory are integrated on the same type of integrated circuit. A microcontroller is associated with each of these memories. In order that the independence of operation of these microcontrollers may be ensured, they are each provided with time delay circuits whose role is to maintain the read or write operation of one microcontroller when another is selected.

Abstract: An HV transistor integrated in a semiconductor substrate with a first type of conductivity, comprising a gate region included between corresponding drain and source regions, and being of the type wherein at least said drain region is lightly doped with a second type of conductivity. The drain region comprises a contact region with the second type of conductivity but being more heavily doped, from which a contact pad extends.

Abstract: A manufacturing process providing a zener diode formed in an N-type well housing a first N-type conductive region and having a doping level higher than the well, and a second P-type conductive region arranged contiguous to the first conductive region. The first conductive region is connected, through a third N-type conductive region having the same doping level as the first conductive region, to a conductive material layer overlying the gate oxide layer to be protected. The third conductive region, the well, and the substrate form an N+/N/P diode that protects the gate oxide layer during manufacture of the integrated device from the deposition of the polycrystalline silicon layer that forms the gate regions of the MOS elements.

Abstract: A method including: forming doped regions on a monocrystalline substrate; growing an epitaxial layer; forming trenches in the epitaxial layer extending to the doped regions; anodizing the doped regions in an electro-galvanic cell to form porous silicon regions; oxidizing the porous silicon regions; removing the oxidized porous silicon regions to form a buried air gap; thermally oxidizing the substrate to grow an oxide region from the walls of the buried air gap and the trenches, until the buried air gap and the trenches themselves are filled.

Abstract: An integrated oscillator and associated methods are provided for providing clock signals. The integrated oscillator preferably includes a micro-mechanical oscillating circuit for providing an oscillating clock signal. The micro-mechanical oscillating circuit preferably includes a support layer, a fixed layer positioned on a support layer, remaining portions of a sacrificial layer positioned only on portions of the fixed layer, and an oscillating layer positioned on the remaining portions of the sacrificial layer, overlying the fixed layer in spaced relation therefrom, and extending lengthwise generally transverse to a predetermined direction for defining a released beam for oscillating at a predetermined frequency. The spaced relation is preferably formed by removal of unwanted portions of the sacrificial layer.

Abstract: A method and device decode a compressed image, and in particular, an image compressed according to the MPEG standards, especially a bidirectional image. To perform two successive decodings of a bidirectional image, the address of the data packet containing the start-of-image identifier of the bidirectional image is tagged, and the temporal reference of this image is stored. After the first decoding, the stored address of the memory is again pointed to and a second decoding is performed after a new detection of the temporal reference of the image.

Abstract: A PET decoder for an ATM network has a modular architecture including a processing unit having various memories and a processing pipeline for constructing from a block of m data of a certain number of bits, a square matrix A based on a vector D of relative points over the Galois field. The processing pipeline also decomposes by triangular factorization the square matrix A and solves the subsystem of equations by simple substitution. The decoder also includes a control unit interfacing with the ATM network, a programmable parallel processor, a random access memory and the processing unit.

Abstract: A Pfield operation defined according to the Montgomery method by Pfield(A, B)N=A*B*I mod N, where I is a determinable error, is implemented in a processor. The least significant word of the data elements A and N which are stored in elementary sub-registers are shifted twice. This eliminates delay cells in a processor used for executing the Pfield operation.

Abstract: A pair of equivalent controlled impedance buffers are connected in a push-pull configuration to a transformer primary coil. A pair of equivalent pre-drivers are connected to the pair of buffers. Each pre-driver receives a driver input signal and outputs a buffer input signal and a proportional flyback compensation signal. Each buffer receives the buffer input signal generated from one of the pre-drivers for buffered output as a line driver signal to the primary coil which induces a flyback voltage effect in each buffer. Each buffer further receives the flyback compensation signal generated from the other one of the pre-drivers, with the buffer operating to cancel the flyback voltage effect induced in that buffer using the flyback compensation signal received from the other one of the pre-drivers. An adjustment circuit further outputs an adjustment signal for application to an adjustable current source.

Abstract: In a EEPROM memory architecture organized into word columns that includes n memory cells per word column, there is, for each word of the column, one diffusion line to connect sources of the memory cells to a ground connection transistor using a source line. A word read access includes simultaneously selecting the word accessed in a read mode in a first group of memory cells, and an additional word in the second group of memory cells. Each column has n bit lines ranked 0 to n−1, each connected to the same ranked cells in the first group of memory cells.

Abstract: An integrated electronic device having a first charge pump, intended to drive a first line having a high capacitive load, and a second charge pump having a high current pumping capacity and intended to drive a second line, a controlled switch is interposed between the outputs of the two pumps, such as to connect the output of the high current capacity pump to the first line, to charge the first line quickly to the preset voltage, without the first charge pump being oversized. When the voltage present on the first line becomes greater than the voltage at the output of the second charge pump, owing to the current required by the second line, the switch is opened. A common phase generator which drives both the pumps is also provided.

Abstract: A method of forming source and drain regions for LV transistors that includes the steps of forming sacrificial spacers laterally to LV gate regions; forming LV source and drain regions in a self-aligned manner with the sacrificial spacers; removing the sacrificial spacers; forming HV gate regions of HV transistors; forming gate regions of selection transistors; forming control gate regions of memory transistors; simultaneously forming LDD regions self-aligned with the LV gate regions, HV source and drain regions self-aligned with the HV gate regions, source and drain regions self-aligned with the selection gate region and floating gate region; depositing a dielectric layer; covering the HV and memory areas with a protection silicide mask; anisotropically etching the dielectric layer, to form permanent spacers laterally to the LV gate regions; removing the protection silicide mask; and forming silicide regions on the LV source and drain regions and on the LV gate regions.

Abstract: A method is for self-test and correction of errors due to a loss charge for a flash memory including an array or matrix of cells (bits), organized in rows and columns, erasable and programmable by whole sectors in which the matrix is divided.

Abstract: A low noise adaptive bias circuit is provided for a low noise bipolar junction input transistor having an emitter degeneration inductance, of an integrated high frequency functional circuit driven by the collector current of the input transistor. The bias circuit includes a shunt line connecting the base node of the input transistor to a first supply node of opposite sign of that of a second supply node to which is coupled, through the degeneration inductance, to the emitter of the input transistor. The shunt line includes a bias current generator dependent, in an inversely proportional manner, on the current gain of the input transistor, and a resistance dependent, in a directly proportional manner, on the current gain of the input transistor.

Abstract: In a junction isolated integrated circuit including power DMOS transistors formed in respective well regions or in an isolated epitaxial region on a substrate of opposite type of conductivity, circuits are formed in a distinct isolated region sensitive to oversupply and/or belowground effects. These effects are caused by respective power DMOS transistors coupled to the supply rail or ground. These effects are alternatively controllable by specifically shaped layout arrangements, and may be effectively protected from both effects. This is achieved by interposing between the region of sensitive circuits and the region containing the power DMOS transistors for which the alternatively implementable circuital arrangements are not formed, the region containing the power DMOS transistors coupled to the supply rail or to a ground rail for which the alternatively implementable arrangements are formed.

Abstract: A six transistor static random access memory (SRAM) cell with thin-film pull-up transistors and method of making the same includes providing two bulk silicon pull-down transistors of a first conductivity type, two active gated pull-up thin-film transistors (TFTs) of a second conductivity type, two pass gates, a common word line, and two bit line contacts. The bulk silicon pull-down transistors, two active gated pull-up TFTs, and two pass gates are connected at four shared contacts. In addition, the two bulk silicon pull-down transistors and the two active gated pull-up TFTs are formed with two polysilicon layers, a first of the polysilicon layers (poly1) is salicided and includes poly1 gate electrodes for the two bulk silicon pull-down transistors. A second of the polysilicon layers (poly2) includes desired poly2 stringers disposed along side edges of the poly1 gate electrodes, the desired poly2 stringers forming respective channel regions of the pull-up TFTs.

Abstract: A transconductor includes a differential stage formed by a pair of input transistors, and a resistive line of degeneration connecting the sources of the input transistors. A bias current generator is coupled between the source of each input transistor and ground. The resistive line of degeneration is formed by one or more transistors connected in series, the gates of which are coupled to a voltage reference. The voltage reference is at least equal to the common mode voltage of the differential stage. The one or more transistors forming the resistive line of degeneration are sized to operate in the triode region.

Abstract: A semiconductor power device comprising an insulated gate bipolar transistor, of the type which comprises a semiconductor substrate with a first type of conductivity and an overlying epitaxial layer with a second type of conductivity, opposite from the first, and whose junction to the substrate forms the base/emitter junction of the bipolar transistor, has the junction formed by a layer of semiconductor material with conductivity of the second type but a higher concentration of dopant than that of the epitaxial layer. Furthermore, the device has the epitaxial layer with conductivity of the second type provided with at least two zones at different dopant concentrations, namely a first lower zone being part of the junction and having a higher dopant concentration, and a second upper zone having a lower concentration.

Abstract: A redundancy UPROM cell includes at least one memory element of EPROM or Flash type, having a control terminal and a conduction terminal to be biased, an inverter register connected to the memory element by at least one MOS transistor. Such cell also includes a pass transistor which connects said conduction terminal to a data line and a pull-up transistor which connects the data line to a supply voltage reference. The UPROM cell has the great advantage to result in smaller dimensions in comparison with the cells of known type, at equal final functions and performances being assumed.