Abstract: A circuit for regulating the gain of a variable differential gain amplifier. In one embodiment, a fully differential amplifier amplifies the outputs of the variable gain amplifier. The outputs of the fully differential amplifier are applied to a three input comparator so that if either of the outputs are greater than a reference voltage, a control signal is generated which is used to regulate the gain of the variable gain amplifier. In other embodiments, an analog OR function is used as an input to a conventional two input comparator in place of the three input comparator. In another embodiment, outputs of the variable gain amplifier are passed through switches to a scaling circuit which either voltage divides or amplifies and combines the outputs before application to a comparator. In each case, known asymmetries can be compensated for by independent gain control of each of the outputs of the variable gain differential amplifier.

Abstract: A circuit for minimizing the current spikes in through the stator coils in a brushless dc motor is disclosed. The circuit includes a voltage amplifier for receiving an input signal voltage and a feedback voltage, a compensation circuit for compensating the output of the voltage amplifier, a second voltage amplifier for amplifying the compensated output, a switch for selectively connecting compensated output to the stator coils, and a conductive path for discharging the compensation circuit when the switch is not conducting. The conductive path can be a transistor or a transistor in series with a voltage reference device. The invention reduces the commutation noise and the dynamic power requirement in a brushless direct current motor.

Abstract: The present invention relates to a method of manufacturing an electrically programmable memory cell with a lateral floating gate with respect to the control gate, including the steps of forming an insulated control gate on an active area; forming a thin insulating layer around the control gate; successively depositing a thin layer of a conductive material and a layer of an insulating material; anisotropically etching the insulating material to form spacers of this material; and removing the portions of the thin conductive layer which are not coated with the spacers.

Abstract: A write head is described having a switchable damping resistance coupled in parallel with an inductor. The damping resistance is decoupled from the inductor by rendering a transistor nonconductive when a direction of current in the inductor changes. The damping resistance is then coupled to the inductor before oscillations begin in the current in the inductor. The decoupling of the damping resistor eliminates power dissipation in the damping resistor during a change in the direction of current in the inductor.

Abstract: A transistor including an epitaxial layer with a first conductivity type, a base buried region with a second conductivity type, and a sinker base region with the second conductivity type which extends from a main surface of the transistor to the base buried region, and delimits, together with the base buried region, emitter fingers in the epitaxial layer. The transistor further includes an emitter buried region with the first conductivity type and a doping level which is higher than that of the epitaxial layer. The emitter buried region is embedded in the epitaxial layer in a position adjacent to the base buried region. A sinker emitter region having the first conductivity type and a doping level which is higher than that of the epitaxial layer and extends from the main surface to the emitter buried region inside the emitter fingers.

Abstract: A method of vapor phase epitaxy deposition of silicon on a silicon substrate on or in which exist areas containing dopants at high concentration, among which is boron, while avoiding a selfdoping of the epitaxial layer by boron, including the step of introducing a chlorinated gas, before the epitaxial deposition step, to etch the substrate across a thickness smaller than 100 nm.

Abstract: A circuit structure for semiconductor devices which are integrated on a semiconductor layer is provided. The structure comprises at least one MOS device and at least one capacitor element that has a bottom and a top electrode. The MOS device has conduction terminals formed in the semiconductor layer, as well as a control terminal covered with an overlying insulating layer of unreflowed oxide. The capacitor element is formed on the unreflowed oxide layer.

Abstract: A process for the manufacture of a non-volatile memory with memory cells arranged in word lines and columns in a matrix structure, with source lines extending parallel and intercalate to said lines, said source lines formed by active regions intercalated to field oxide zones, said process comprising steps for the definition of active areas of said columns of said matrix of non-volatile memory cells and the definition of said field oxide zones, subsequent steps for the definition of the lines of said matrix of non-volatile memory cells, and a following step for the definition of said source lines.

Abstract: A control or adjusting circuit for a load, a desired signal is compared to an actual signal corresponding to the state of the load, and a PWM control signal is generated in a control signal generating circuit in accordance with the comparison result. The control signal opens and closes a current switch coupled to the load. For forming the PWM control signal, the contents of a ramp counter are compared to the contents of an up/down counter by means of a digital comparator. To obtain fast approximation of the two signals to each other in the case of strong deviations between the desired signal and the actual signal, the up/down counter is subjected to relatively rapid counting in case of high control deviations as compared to low control deviations. To this end, the up/down counter is operated with a clock signal of variable frequency that is produced by a voltage-controlled oscillator as a function of the difference between the desired signal and the actual signal.

Abstract: A method of operating a cache memory is described in a system in which a processor is capable of executing a plurality of processes, each process including a sequence of instructions. In the method a cache memory is divided into cache partitions, each cache partition having a plurality of addressable storage locations for holding items in the cache memory. A partition indicator is allocated to each process identifying which, if any, of said cache partitions is to be used for holding items for use in the execution of that process. When the processor requests an item from main memory during execution of said current process and that item is not held in the cache memory, the item is fetched from main memory and loaded into one of the plurality of addressable storage locations in the identified cache partition.

Abstract: A circuit and method is disclosed for a memory cell for a static random access memory. The memory cell includes a pair of cross-coupled CMOS logic inverters that are connected together to form a latch, and a pair of p-channel transmission gate transistors that are connected to the logic inverters for selectively providing access to the latch. The layout of the memory cell includes a rectangular active area in which the p-channel transistors of the memory cell are located. The rectangular active area abuts a similar active area of an adjacent memory cell along a row of memory cells so as to form a single rectangular active area for the p-channel memory cell transistors. The rectangular active area reduces the occurrence of fabrication-related phenomena that adversely effect the performance of the memory cell.

Abstract: A substantially noise-free data input buffer for an asynchronous device, such as a static random access memory (SRAM). The input buffer generates either a logical true or complement output signal representation of a data input signal and includes timing circuitry to delay an edge transition on the output signal for a predetermined period of time in response to a signal edge transition appearing on the data input signal. The input buffer further includes edge transition detection (ETD) circuitry for generating an initialization signal in response to the generation of the data output signal.

Abstract: The present invention relates to a power dimmer of a load, powered by an a.c. voltage, of the type including a bidirectional switch associated in series with the load, the switch being normally closed and controllable to be opened upon each halfwave of the a.c. voltage.

Abstract: A non-volatile memory device organized with memory cells arranged by rows and columns in a matrix structure comprising source lines for memory cell groups. A switch is set between at least two rows or columns or source lines, which has two no pilotable terminals connected respectively to each one of the two rows or columns or source lines and a pilotable terminal connected to a logic circuitry. The switch allows a precharge of one of the two rows or columns or source lines by capacitive means associated to a each one of the two rows or columns or source lines after the other of the two rows or columns or source lines is connected to a higher voltage than that of said one of the two rows or columns or source lines.

Abstract: A method for the in-writing verification of the threshold value of the multilevel cells suitable to memorize n bits each, that provides for the utilization of a sense amplifier containing a respective successive approximation register. An output signal of a comparison circuit provides for the loading of the datum to be programmed in the cell being selected, after which a programming pulse is applied and the comparison between the reference current corresponding to said datum and the current that flows in the cell is carried out. The application of the programming pulse and the performance of the comparison are then repeated until it is verified that the current of the cell is smaller than the reference current.

Abstract: An inertial sensor has a sensing element formed on one surface of a chip of semiconductor material and which is movable with respect to the chip. The sensing element is enclosed in a sealed hollow structure, in which the hollow structure includes a metal wall disposed on the surface around the sensing element, and a closure plate fixed to the wall.

Abstract: A device controller controls access to a device, such as a television, having a power input for receiving power and a data input for receiving control data. When in standby mode, the device controller disconnects the device from a power source, such as the AC mains of the building in which the device is situated. As a result, in standby mode only the device controller is powered, which uses much less power than prior art devices in standby mode. The device controller includes an input device structured to provide control data based on control instructions received from a user, a power switch coupled between a power source and the device power input, and a data coupler coupled to the device data input and structured to convert electrical data into non-electrical data and back to the electrical data for delivery to the device data input.

Abstract: A dynamic random access memory (DRAM) device is disclosed. The DRAM device includes a memory cell array having a twisted bit line architecture. The memory cell array includes at least one pair of redundant rows of memory cells. Redundant row decode circuitry is capable of configuring the pair of redundant rows to replace any one row of memory cells having a defect. Each pair of bit lines is coupled to a distinct memory cell from each redundant row of the redundant row pair so that both the true and complement version of a data value is maintained by the redundant row pair. Rows of reference cells are disconnected and/or disabled during a memory access operation involving the redundant row pair. The use of a pair of redundant rows of memory cells to replace a single row of memory cells having a defect substantially reduces the complexity of decode circuitry for enabling the rows of reference cells.

Abstract: Two improved process steps of eliminating cracks within TiN and/or BPSG layers after the RTP process are provided. The first is to provide a low deposition power, preferably below 6.5 KWH, and a high process pressure, preferably above 5.6 mTorr, to the TiN layer. No crack is found for this improved TiN deposition process when the RTP temperature rises from 450° C. to about 700° C. The second is to provide a low RTP temperature, preferably below 595° C., to the semiconductor wafer. No crack, again, is found by using this low RTP temperature.

Abstract: A field-effect transistor structure wherein a single patterned thin film semiconductor layer: is monocrystalline, and epitaxially matched to and dielectrically isolated from an underlying body region, in channel locations; and is polycrystalline in source/drain locations which abut said channel locations.