Abstract: A motor and drive mechanism having a drive hub which positively locks to a core for a ribbon roll, and a drag hub which also positively locks to a core for a ribbon roll. A ribbon roll has a core formed of concentric cylindrical shells separated from one another with a ribbon wound about the outer shell and one or more coding marks are provided on this shell to indicate both the printer control system and, to a visual observer, information specific to the ribbon.

Abstract: A spread spectrum communication system having a plurality of transmitters at remote locations capable of transmitting information to one or more receivers during a plurality of information time durations. A message structure interposing the plurality of information time durations with a plurality of preamble time durations, during which time the receiver detects message transmission, is also provided.

Abstract: The present invention relates to a housing for an optical coupler. The housing includes a primary protective body having a receiving space therein, wherein the coupled portion of the coupler is positioned. A support material at least partially about the coupled portion of the coupler extends in the receiving space to the primary protective body. The support material is resilient and has an index of refraction less than that of the coupled portion of the coupler.

Abstract: An information retrieval system for extracting information from a pair of substantially coherent electromagnetic waves represented by phase differences therebetween each of which is incident on a photodetector, and having a demodulator which receives the photodetector output signal and which also receives a reference signal. The reference signal is obtained through use of a phase shift detector which receives the photodetector signal to determine certain phase shifts occurring therein and provides this information to a reference signal supply to adjust the phase of its output signal which then serves as the reference signal for the demodulator.

Abstract: An improvement in a switching state retention circuit of adding a shunt capacitance across an inverter output in a selectable feedback loop. The circuit has a controlled inverter connected to both the selectively connected feedback loop and an output inverter. The shunt capacitance is across an inverter in the feedback loop to control propagation delay therearound without slowing state changes at the output of the circuit.

Abstract: A test system for determination of the integrity of interconnections between integrated circuits based on test circuit portions provided in such integrated circuits which are subject to signals from the inputs that might vary in value because of faulty interconnections. The values on such inputs are set, in the absence of input signals reaching them, by switchable resistances in the corresponding test circuit portions each of which can couple a predetermined signal value to a corresponding input, but which can also be overridden by signals supplied to that input across the corresponding interconnection from a source thereof.

Abstract: A magnetic thin-film memory in a monolithic integrated circuit using inductive sensing of the memory states occurring therein.

Abstract: A method for storing selected magnetic states in magnetic bit structures so as to assure establishment of the desired state therein. A first word line current, used for storing a magnetic state, is followed by providing a second word line current. The second line current assures establishment of the desired state in the magnetic bit structure by overcoming any pinning of a magnetic wall.

Abstract: A delay timer formed by a sequence of inverters alternating in type, some with single and some with multiple outputs each having an output connected to the input of the next. An output from each of the multiple output inverters is connected to the timer output.

Abstract: A method for sensing magnetic states of magnetic bit structures formed of separated double layer, magnetoresistive, ferromagnetic memory films through providing a word line current in a direction which results in a magnetic field due thereto, in the memory films of these bit structures, that is oriented in a direction opposite a common direction followed at least partially by orientations of edge magnetizations in these films that are parallel to the edges thereof, and sensing a change in electrical resistance of these bit structures as a result of that current.

Abstract: A bipolar transistor having higher conductivity semiconductor material in the substrate as compared to the active base region to provide charge generation disturbance protection.

Abstract: A semiconductor junction related structure to control sensitivity of signal processing systems to signals of greater versus smaller values.

Abstract: A circuit arrangement is provided for a command source directing operation of a subsequent circuit. This command source circuit, based on using cross-coupled transistors, is electrically isolated from the subsequent circuit when no commands are being generated, and provides an output of constant polarity for input command signals of either constant or varying polarity.

Abstract: A data communication system having improved error correction and detection capabilities includes an encoder which converts each input word containing three binary message bits to an eight-bit binary code vector which contains exactly four "1's" and four "0's", and thus has a fixed "weight" of 4. In addition, the same symbol (either a "1" or "0") is consecutively repeated in the code vector no more than two times. The code vector is transmitted from a transmitter to a receiver, and the eight-bit received vector is decoded by a decoder to produce an output word containing three message bits. The decoder detects errors in received vectors by checking the weight of the received vector, by checking syndrome based upon predetermined combinations of bits of the received vector, and by performing a parity check on two selected bits of the received vector which should be unequal.

Abstract: An interface circuit to couple logic signals from a logic gate of one kind of logic family to a logic gate of another operating at different logic state voltages, where a latch circuit is used with the first of two cascaded inverters to provide the desired interface circuit signal characteristics. One inverter is provided with a supply reduction threshold means as is another inverter in the latch so that the two inverters perform substantially similarly to one another. The latch allows independent adjustments of opposite direction logic level transitions to provide a desired noise margin.

Abstract: A frequency shift keyed (FSK) data transmission system utilizes existing power lines to transmit data by superimposing a high frequency FSK signal on the power line carrier. A transmitter includes a phase locked loop which is locked on the power line carrier frequency and which synthesizes the FSK signal and a timing signal which defines the data rate of the transmitter. As each bit is transmitted, an oscillator control signal either speeds up or slows down the loop oscillator temporarily to produce the FSK signal. A receiver demodulates the data transmission from the power line by separating a power line carrier frequency component and a FSK signal component. The receiver includes a phase locked loop which locks onto the power line carrier frequency and which synthesizes a reference frequency and a timing signal which defines the data rate of the receiver.

Abstract: A CMOS window detector provides outputs which indicate whether an input voltage is within a voltage "window". The window detector includes a bias circuit and first and second inverter circuits. A bias current is established by the bias circuit as a function of a reference voltage. The first and second inverter circuits each include a current mirror field effect transistor (FET) and a current control FET connected in a series current path. The current mirror FETs are connected to the bias circuit to provide two different mirror currents. The mirror currents are a function of the bias current and the current mirror FET channel shape factors. The input voltage signal is applied to the gates of the current control FETs of the first and second inverters. The window voltage level of each inverter circuit is independent of the other inverter circuit and is determined as a function of the mirror current and channel shape factor of the current control FET.

Abstract: A phase locked loop provides limited phase correction when in lock in order to minimize the effects of noise in the periodic input signal to which the loop is locked. The phase locked loop includes a voltage controlled oscillator (VCO), a timing generation divider, a phase detector, a lock detector and an oscillator control circuit. The phase detector provides an output based upon the phase difference between rising edges of the input signal and a loop synthesized signal which is derived by the divider from an oscillator output signal. A window signal, which begins slightly before and ends slightly after an anticipated rising edge of the input signal, is also derived from the oscillator output signal. The lock detector provides a lock detect signal which indicates whether the loop is in lock. The oscillator control circuit provides an oscillator control voltage based upon the phase detector output signal, the window signal, and the lock detect signal.

Abstract: Lens arrangements for integrated circuits having a plurality of optical transducers is provided. A method for prefabricating such an arrangement is also disclosed.

Abstract: A power up reset pulse generator circuit provides a reset pulse to initialize the states of logic elements in a low power field effect transistor (FET) integrated circuit. The reset pulse generator includes a pair of P-channel enhancement FETs and a first capacitor connected in a series charging path between V.sub.DD and V.sub.SS power supply terminals of the integrated circuit. A second capacitor, and a pair of N-channel enhancement FETs are connected in a second series charging path between the V.sub.DD and V.sub.SS terminals. The second capacitor is connected between the V.sub.DD terminal and an output node, at which the reset pulse is provided. Before power is applied, the first and second capacitors are uncharged and all four FETs are off. When power is applied and the potential between V.sub.DD and V.sub.SS terminals exceeds twice the P-channel threshold voltage, the P-channel FETs turn on, thereby allowing the first capacitor to begin charging. In the meantime, the voltage at the output has followed V.