Abstract: A CMOS window detector provides an output signal which indicates the relationship of an input signal to a voltage "window" as a function of the previous output signal. The window detector includes first and second current source circuits and first and second inverter circuits. A bias current is established in each current source circuit as a function of a different reference voltage. The first and second inverter circuits each include a current mirror field effect transistor (FET) and a current control FET connected in a series current path. The current mirror FET of each inverter circuit is connected to its respective current source circuit and establishes a current in the inverter current path equal in magnitude to its respective bias current. The input signal is applied to the gates of the current control FETs. Each current control FET changes conductivity state when the input signal reaches the reference voltage level used to establish the respective inverter current flow.

Abstract: An electronic switching circuit is provided for controlling transfer of electrical power from an alternating polarity electrical power supply to a load means through use of a field-effect transistor device as a primary power controlling element. The circuit also is arranged such that the alternating polarity electrical power supply provides power for operating further circuit components used to direct operation of the primary power controlling element. Certain of these further circuit elements can be prevented from drawing electrical power in certain situations.

Abstract: A frequency shift key receiver includes a phase velocity sign detector which detects whether a FSK modulated input signal has a frequency (f.sub.FSK) which is greater than or less than a reference frequency (f.sub.0) of a REF signal. The phase velocity sign detector includes a sequence generator which generates a two bit binary code which represents the phase angle between the FSK and REF signals. The sequence of the code indicates the sign of the phase velocity between the FSK and REF signals. The phase velocity sign detector includes a sequence detector which provides an output signal indicating whether the FSK signal has a frequency greater than or less than the REF signal based upon the sequence of the code from the sequence generator. The phase velocity sign detector demodulates the FSK signal in the digital domain using circuitry which is completely integrable on a monolithic integrated circuit chip.

Abstract: Temperature variation of the input bias current of a monolithic integrated circuit junction field-effect transistor (JFET) is provided by a compensation diode formed concurrently with the JFET in the monolithic integrated circuit. The compensation diode has a first region which is formed concurrently with the channel region of the JFET, and a second region which is formed concurrently with the gate region of the JFET. The areas of the first region and the channel region are equal. In addition, the area of the junction formed by the first and second regions of the compensating diode is equal to the area of the junction formed by the gate and channel regions of the JFET. The first region of the compensation diode is electrically connected to the gate region of the JFET so that reverse leakage current of the compensation diode compensates and tends to cancel the reverse leakage current of the gate-channel junction of the JFET.

Abstract: A monolithic integrated circuit is provided capable of providing charge packets which are selectable multiples of other charge packets. This capability is provided by a charge-coupled device floating gate regenerator and an associated MOS capacitive region.

Abstract: A frequency shift key demodulator produces an output data stream based upon whether a FSK modulated input signal has a frequency (f.sub.FSK) which is greater than or less than a reference frequency (f.sub.0) of a reference (REF) signal. The demodulator includes a sequence generator which generates a two bit binary code which represents the phase angle between the FSK and REF signals. The sequence of the code indicates the sign of the phase velocity between the FSK and REF signals. The demodulator also includes first and second sequence detectors, first and second integrating shift registers, and a decision circuit. The first sequence detector provides an output signal to the first shift register indicating that the FSK signal has a frequency less than the REF signal based upon detection of a first predetermined sequence of the code from the sequence generator.

Abstract: A monolithic integrated circuit is provided in which signals from concurrently operating information sources are each provided to a corresponding signal processing cell in an array thereof. These cells can each communicate directly with surrounding nearest neighbor cells both to and from. Each such signal processing cell is capable of being directed in parallel to perform selected signal processing operations including operations involving data from many cells. Communications between cells can be effected using charge coupled devices, and the signal processing operations in a cell can be performed by a floating gate regenerator.

Abstract: An electrically erasable, programmable read-only-memory cell compatible with a high voltage value generator for writing and erasing in the cell being in the same chip.

Abstract: A voltage controlled current source provides a load current through a load impedance which is a function of an input voltage and is independent of the impedance value of the load impedance. The voltage controlled current source includes a high input impedance unity gain instrumentation amplifier and a resistor connected in series with the load impedance so that current flows through the resistor and the load impedance. The instrumentation amplifier receives the input voltage at its inverting input and receives a load voltage representing the voltage across the load impedance produced by the load current at its noninverting input. The instrumentation amplifier subtracts the input voltage at the inverting input from the load voltage at the noninverting input and multiplies by a gain of one to produce an output voltage at its output. The resistor and the load impedance are connected in series between the output of the amplifier and a reference voltage (e.g.

Abstract: A threshold voltage control circuit controls the threshold voltages of one or more field-effect transistors (FETs) of an integrated circuit. The threshold voltage control circuit includes a reference (FET) which is electrically connected to the other FETs so that the threshold voltage of the reference FET determines the threshold voltages of the other FETs. A bias voltage is applied to a gate of the reference FET and a current path is established between first and second supply terminals. This current path includes the drain and source of the reference FET. The current flowing in the current path is a function of the bias voltage applied to the gate of the reference FET and the threshold voltage of the reference FET. A high gain, high input impedance amplifier is connected to the current path and provides a threshold control signal to the reference FET (and the other FETs) which is a function of the current in the current path.

Abstract: Apparatus for identifying intended crossing events of a preselected value of an analog signal is disclosed. The apparatus further identifies whether the signal is rising or falling during those crossing events.

Abstract: A voltage summation circuit receives a series of input voltage signals and provides an output voltage signal which represents a summation of the input voltage signals. The voltage summation circuit includes first and second capacitors, a current mirror, and an input switch. During a first clock phase of each cycle in which an input voltage signal is received, the input switch connects the first capacitor to the input to charge the first capacitor as a function of the input voltage signal. During a second clock phase the input switch connects the first capacitor to the current mirror to discharge the first capacitor. The current mirror is connected to the second capacitor, so that the change in charge on the first capacitor during the second clock phase results in a similar change in charge on the second capacitor. The charging and discharging of the first capacitor during the first and second clock phases is repeated for each input voltage signal.

Abstract: An electronic switching circuit is provided for controlling transfer of electrical power from an alternating polarity electrical power supply to a load means through use of a field-effect transistor device as the primary power controlling element. A bypass means is used to provide shunting between one of the terminating regions of the field-effect transistor device and its substrate in situations where the field-effect transistor device is passing substantial current.

Abstract: A phase correction system is disclosed for adjusting a phase relationship of periodic data samples, based on a level crossing detector identifying certain data samples in connection with a preselected value.

Abstract: An expected level determination system is disclosed for determining the expected level of incoming analog signals at the receiver end of a digitally based communications channel. This is accomplished by a feedback loop based on apportionment.

Abstract: An integrated circuit stress transducer system including signal processing circuitry responsive to signals from semiconductor stress sensors where the processing circuitry output signals are compensated for sensor stress sensitivity variations.

Abstract: An improved band gap voltage regulator provides a stable, temperature-independent, output voltage which is approximately equal to the band gap voltage of silicon or a function thereof. The circuit utilizes integrated circuit resistors and bipolar transistors. Semiconductor process variations which affect transistor base-emitter junction voltage and thus would otherwise affect the value of the output voltage are compensated by a base pinch resistor.

Abstract: A communications channel monitoring system is disclosed for digitally based communication channels carrying signals corrupted by noise. The monitor system provides a signal indicative of the expected value of the communication channel signal if uncorrupted by noise and provides a signal indicating the extent of any such corruption.

Abstract: An offset adjustment system is disclosed to correct for the presence of a constant or slowly varying additive component in an incoming analog baseband signal at the receiver end of a digitally based communications channel based on a level crossing detector identifying certain data samples in connection with a preselected value.

Abstract: An electronic imager arrangement is provided in which the time duration for sensing radiation is established by determining the amount of radiation already sensed.