Abstract: A digital test system for generating a test signal in the form of an amplitude and/or phase modulated sinusoidal signal at a given carrier frequency is disclosed. Arbitrary amplitude and phase modulation functions may be selected and are provided to the system in the form of digitally encoded data streams. The system does not require a digital multiplier. A signal in the form of an unmodulated carrier signal may also be generated.

Abstract: A system for increasing the accuracy and resolution of an ADC comprising a digital filter connected to the output of the ADC, a system clock for providing a digital filter clock signal, a low/pass filter/amplifier for generating a large-scale, rapidly varying dither signal fdrom the digital filter clock signal, and a summing circuit for adding the dither signal to a test signal connected to the input of the ADC.

Abstract: A color image processing system is described which provides more realistic hard copy color images from composite video system input signals than previously available. The image processing system includes a synchronization separator 20 which operates to separate the synchronization pulses from the analog video information supplied to it. The analog video information is then converted to digital form by an analog-to-digital converter. The converter operates under control of a time base generator 100, including a programmable delay line 300, which receives synchronization pulses from the synchronization separator, and following a programmable time delay supplies a control pulse to the converter to cause it to sample the analog waveform and convert it to digital format. Once the signal is digitized, it is converted from an additive color system to a subtractive one end enhanced before being supplied to the color plotter 8.

Abstract: Apparatus for delaying an electrical signal includes a sequence of stages, each for delaying the signal. A coarser stage delays the signal by multiples of a predetermined fundamental delay interval and a finer stage provides for fine adjustment of the delay. The fine stage includes an integral number N of delay elements, the total providing a delay interval greater than the fundamental delay interval, whereby the fine delay intervals compensate for fabrication tolerances to enable accurate calibration of the combined system by post-fabrication measurement. In one implementation each delay stage includes a tapped transmission line to provide delay intervals, in another a ramp generator is used.

Abstract: A method of calibrating a feed forward, DAC post-correction system. The method includes fitting the Walsh co-efficiencts of a DAC transfer function to a straight line in the log domain. The deviation of these terms in the log domain is utilized to compute Walsh correction terms for use in the post correction system.

Abstract: An image processing system includes a synchronization separator 20 which operates to separate the synchronization pulses from the analog video information supplied. The separator includes an amplifier with a pair of input terminals. The video is coupled to one of the input terminals and a feedback loop coupled between an output terminal and the other input terminal. In this manner the negative synchronization pulses may be amplified while the positive video signals are limited. The extracted sync signal is used to control an analog-to-digital converter 70. The analog video information is then converted to digital form by an analog-to-digital converter. The converter operates under control of a time base generator 100, including a programmable delay line 300, which receives synchronization pulses from the synchronization separator, and following a programmable time delay supplies a control pulse to the converter to cause it to sample the analog waveform and convert it to digital format.

Abstract: Information indicative discrete events of interest imbedded in raw data are globally classified, or filtered with respect to scale and changes in the scale of observation to effect intelligent perception of phenomena. Large scale components are classified as events while small scale components of an identified event designate points of occurrence of the event. The invention has broad application in artificial intelligence and signal processing wherein perceived discrete events, including minima, maxima, inflections, cusps, and discontinuities have a significance other than as noise. Methods and apparatus are described which utilize the subject invention in signal processing applications.

Abstract: A circuit technique for stabilizing the timing of signals at an output node of a gate, despite substantial variations in temperature. In a gate having a switching portion and an emitter follower, the temperature-dependence of the gate delay within the switching portion may be offset by suitable control of the temperature characteristics of the load current source supplying the emitter follower output node. The load current source comprises a current source resistor, a current source transistor having its collector coupled to the output node, and a reference voltage source. The voltage source, rather than having a zero temperature coefficient as in known temperature-compensated configurations, is configured to have a temperature coefficient chosen to provide a temperature dependence in the delay through the emitter follower that offsets the temperature dependence of the delay through the switching portion so that the total gate delay is substantially temperature-independent.

Abstract: A high speed voltage comparator circuit is disclosed which accepts a wide range of input potentials CBO1 and compares them with four potential levels CRH, CRL, CRIH, and CRIL. Each comparator includes input transistors Q103 and Q104, one of which is connected to the reference potential and the other is connected to the unknown potential. The emitters of the input transistors Q103 and Q104 are connected together through a resistor R105, and each emitter is connected to a current source, Q105 and Q107 respectively. A third current source Q106 is coupled to diodes D101 and D102 which are connected to the emitters of transistors Q103 and Q104 respectively. The difference between the reference potential and the unknown potential will forward bias one of the diodes and reverse bias the other. The resulting difference in emitter current between the input transistors Q103 and Q104 is detected by an output stage to indicate the relative magnitudes of the reference potential and the unknown potential.

Abstract: A plurality of test signal applying and monitoring circuits are coupled to pins of an electronic device being tested to force test stimuli signals onto input pins of the device under test. The response signals are monitored while the device is being tested. Each test signal applying and monitoring circuit includes a node to be coupled to a pin of the device under test, a digitally programmed source for supplying a test signal connectable to the node by a first switch, and a comparison circuit connected to the node by a second switch for indicating the relative amplitude of the response signal with respect to a programmed reference level. The digitally programmed source is included for providing gated voltage-current crossover forcing functions during functional testing to minimize the disturbance when the device being tested is connected and to protect out of tolerance devices. Programmable voltage and current values define a pass window to assure a non-ambiguous go/no-go result during testing.

Abstract: A plurality of signal applying and monitoring circuits are coupled to pins of an electronic device being tested to force test stimuli signals representing logic states or other parameters onto input pins of the device under test. The responses to the stimuli signals are monitored while the device is being tested. Each signal applying and monitoring circuit includes a node to be coupled to a pin of the device under test, a device power supply connected to the node for supplying a test bias signal, a comparison circuit connected to the node for indicating the relative magnitude of the test bias signal with respect to the bias level at the node, and a latch circuit responsive to the output signal produced by the comparison circuit. The device power supply is included for providing test bias signals to test power drain during functional testing. The transitions of the device power supply are monitored and latched for providing a record of the power drain of the device being tested.

Abstract: A plurality of test signal applying and response signal monitoring circuits is coupled to pins of an electronic device being tested to force test stimuli signals onto input pins of the device under test. The response signals are monitored while the device is being tested. Each test signal applying and response signal monitoring circuit includes a node to be coupled to a pin of the device under test, a digitally programmed source for supplying a test signal connectable to the node by a first switch, and a comparison circuit connected to the node by a second switch for indicating the relative magnitude of the response signal with respect to a programmed reference level on a repetitive basis during testing to increase test rate. Other features are also disclosed.

Abstract: A formatting circuit for a high speed integrated circuit test system controls the application of timed data pulses to the input terminals of the device being tested, generates strobe signals to control comparators connected to the output terminals of the device being tested, and provides circuitry to decode error signals received from the device being tested. The formatting circuit routes all critical signal paths to the device under test over separate signal lines, thereby allowing compensation for the different propagation delay of each signal path. The input transitions and output strobe signals for the device being tested are not fixed in time with respect to the system clock, but are referenced to it. This enables drive data cycles and compare data cycles to be less dependent on the system clock, and permits them to overlap and cross test period boundaries.

Abstract: A color image processing system is described which provides more realistic hard copy color images from composite video system input signals than previously available. The analog video information is converted to digital form by an analog-to-digital converter. The converter operates under control of a time base generator (100). The time base generator (100) provides more accurate control over the converter than the system clock signal. The generator (100) receives pulses from the synchronization separator, and following a programmable time delay supplies a control pulse to the converter to cause it to sample the analog waveform and convert it to digital format. The generator (100) employs a delay line (300) to detect the fraction of a system clock period between the sync pulse and the next clock pulse. The specified number of clock pulses are allowed to elapse. Then the delay line (300) is used to provide the necessary further delay.

Abstract: A circuit technique for eliminating history-dependent skew and distortion of signals as they propagate through multiple gate stages in critical timing paths. It has been discovered that spurious effects can be attributed to signal coupling between stages, and that such coupling may be reduced by providing separate threshold voltage supplies for the critical gates. Each of the first and second gate stages comprises first and second transistors having their respective emitters coupled to a common circuit point, a current source coupled to the common circuit point to provide current flow through the transistors, with the relative current flow through said transistors being determined by the relative voltage levels at the respective bases. The output signal is taken from the collector of one of the transistors. First and second threshold voltage sources are coupled to the respective bases of the second transistors of the first and second gate stages.

Abstract: A high voltage analog solid state switch is disclosed which includes a pair of MOS FET's 10 and 20 having commonly coupled sources 11 and 21 and commonly coupled gates 13 and 23. A photovoltaic generator 30 and an opto-coupler 40 are connected in parallel between the commonly coupled gates and sources. The input node is connected to the drain of one transistor 10 while an output node is connected to the drain of the other transistor 20. The switch is turned on by application of light 32 to generator 30 to thereby positively bias the gates 13 and 23 and cause transistors 10 and 20 to conduct. The switch is turned off by application of light 42 to coupler 40 to thereby short the commonly coupled sources 11 and 21 to the commonly coupled gates 13 and 23.

Abstract: An automatic test system for parallel loading of data into pin registers 100 associated with pins of a device being tested includes data bus 130 for transmitting data; an address bus 120 for transmitting addresses; a set of pin registers 100, each having a unique address and each coupled to receive information from the data bus 130; a participate register 150 coupled to data bus 130 and to each of registers 100 for enabling selected ones of registers 100 to receive data from the data bus at the same time; an address decoder 110, 180 connected to the address bus 120, to each of registers 100, and to the participate register 150, for enabling one of the pin registers 100 or the participate register 150 to receive data from the data bus, the data for the participate register 150 comprising the addresses of each of the selected ones of pin registers 100 which are to receive data from the data bus in parallel.

Abstract: A method for statistically calibrating an analog-to-digital converter with an electronic test system. A digital-to-analog converter which has been calibrated by premeasured weighting coefficients with respect to two-state orthogonal signals is excited with two state signals at each input bit which together represent a single signal with uniform amplitude probability with respect to time, and wherein each excitation signal is orthogonal with respect to all other excitation signals. The output of the digital-to-analog converter is detected by the analog-to-digital converter under test. The digital time domain output signals are then mapped into a transform domain to obtain weighting coefficients of each bit of the output response. Finally the transform domain weighting coefficients are weighted by the reciprocal of the premeasured weighting coefficients to obtain the unbiased weight of each bit of the analog-to-digital converter under test.

Abstract: A tri-state driver circuit 10 for selectively driving a node of a device under test by applying and switching between two reference voltages, and for selectively operating at a high impedance output state. Two current sources 16 and 18 provide a bridge current that flows through a diode bridge 20 to establish, at nodes A and B, voltages that equal two reference voltages, DRH and DRL. The diode bridge includes resistors R11 and R16 across which the bridge current is switched to accommodate small voltage swings, and also includes clamp diodes CR3-6 to accommodate large voltage swings. A current switch 22 controls the direction of the bridge current and the selection of which of the two reference voltages appears at node A. A current sink 36, 38, and 40 monitors the average voltage of the diode bridge and adjusts it to equal the average of the two reference voltages.

Abstract: An electrical pulse edge timing adjustment circuit 10 comprising one or more deskew elements 5. In each deskew element, a pulse train is passed through an inverter 20. The falling rate of pulse edges on the inverter output line 21 is controlled by a capacitor 24 and an adjustable current sink 25 which determine the output line capacitance discharge rate. From the output line, pulses are passed to another deskew element which re-inverts the pulses and delays the formerly rising pulse edges. Each current sink is independently adjustable to allow different delays in the rising and falling edges.