Abstract: Method and apparatus are provided for measuring the settling time, relative to a reference time, of an analog signal having a varying amplitude. The apparatus includes a pair of comparators U1 and U2 for comparing the amplitude of the analog signal with first and second reference signals V.sub.Ref 1 and V.sub.Ref 2. The comparators U1 and U2 are connected to edge detector 22 which supplies a reset signal to a second counter 26 whenever the amplitude of the analog signal is not between the first and second reference signals. Oscillator 32 drives counters 25 and 26 which count pulses from oscillator beginning at the reference time and continuing until the second counter 26 contains a predetermined count. Because the second counter 26 is reset by the edge detector 22 whenever the analog waveform exceeds either of the reference signals, the difference between counter 25 and counter 26 at any subsequent time after the waveform has settled will be the settling time of the analog waveform.

Abstract: Apparatus is provided for supplying deskewed signals. The apparatus includes a timing generator (20) for generating a pulse of desired duration, a deskew unit (17) connected to receive a pulse and adjust its width to compensate for previous errors, a differentiation network (15) for dividing the pulse into a leading and trailing edge signal, a plurality of logic gates (80 through 85) for receiving the pair of signals and supplying one of the pair along a set path and the other of the pair along a reset path, a deskew unit (86 and 89) associated with each path for delaying the signals thereon, and a latch (53) coupled to the deskew units to reform the electrical signal. Logic gates (80 through 85) operate under control of a format selector (90).

Abstract: A test system memory architecture for passing parameters and testing dynamic components includes a main memory 15, a mask memory 20, and a definition memory 25, operating under control of a main sequence control memory 18. A corresponding subroutine memory 38, subroutine mask memory 22, and subroutine definition memory 27 operate under control of a subroutine sequence control memory 33. Multiplexing apparatus is used to selectively connect any of these memories to the formatter circuit 10. In addition, the architecture includes a parameter enabling memory 30 which is coupled to the subroutine SCM 33 and a switching means for controlling which of the subroutine memory 38 or main memory 15 is coupled to the formatter circuit 10.

Abstract: A closed loop integrated circuit temperature stabilizer 10 has an on-chip temperature sensor 12 for supplying a voltage indication of temperature to an op amp 22 which maintains chip temperature equilibrium by controlling a load transistor 30 which draws current through on-chip heating means 16.

Abstract: Apparatus is provided for delaying an electrical signal present at a selected node. The apparatus includes a first multiplexer 71 which connects one of eight inputs I.sub.0 -I.sub.7 to an output terminal 75, an adjustable length delay line 72 is coupled between each pair of input terminals I.sub.0, I.sub.7, and the input signal is then supplied to the first input terminal of the multiplexer 71. The delay lines 72 are trimmed to create the desired time delay between input terminal 74 and output terminal 75.For larger adjustments of the time delay for the signal is supplied to input terminal 74 and supplied to another terminal 78 connected to the input terminal I.sub.0 of another multiplexer 61. Logic gates 62-67 are connected between each pair of terminals I.sub.0 -I.sub.6 of the second multiplexer 61. A coarser adjustment of the time delay than achievable with the delay lines 72 is made by switching of an appropriate input terminal of the second multiplexer 61 to the output terminal 69 of the multiplexer 61.

Abstract: In an automatic test system, a dynamically controllable addressing circuit coupled to an address bus and a data bus includes a first register 10 for storing a fixed address, a programmable address register 12 connected to store address information from the data bus when the fixed address in the first register corresponds to address information on the address bus, and a programmable data register 18 connected to store data from the data bus when the address information in the programmable address register 12 corresponds to the address information on the address bus. In the preferred embodiment the address bus and the first register are connected through an exclusive or gate 14 to control the operation of the programmable address register 12. A second exclusive or gate 16 is connected between the address bus and the programmable address register 12 to control the operation of the programmable data register 18.

Abstract: A method for statistically calibrating an analog-to-digital converter with an electronic test system. A digital-to-analog converter which has been calibrated by premeasured weighting coefficients with respect to two-state orthogonal signals is excited with two state signals at each input bit which together represent a single signal with uniform amplitude probability with respect to time, and wherein each excitation signal is orthogonal with respect to all other excitation signals. The output of the digital-to-analog converter is detected by the analog-to-digital converter under test. The digital time domain output signals are then mapped into a transform domain to obtain weighting coefficients of each bit of the output response. Finally the transform domain weighting coefficients are weighted by the reciprocal of the premeasured weighting coefficients to obtain the unbiased weight of each bit of the analog-to-digital converter under test.

Abstract: A microprocessor integrated circuit design has improved partitioning between integrated injection logic (I.sup.2 L) and transistor-transistor logic (T.sup.2 L) in the integrated circuit. An information bus structure incorporating a bidirectional input and output buffer and a bidirectional input and output multiplexer minimizes the number of internal bus lines in the integrated circuit. An improved T.sup.2 - I.sup.2 L interface circuit and structure supplies a T.sup.2 L input to a plurality of I.sup.2 L input stages, each having a restricted cross-sectional area resistor element in the base of an I.sup.2 L input transistor. A storage register in the integrated circuit has a multiplexer portion provided at each flip-flop circuit of the register. A high speed feed forward flip-flop circuit is employed in registers of the integrated circuit where speed is critical. An improved voltage regulator and current source combination in a programmable logic array (PLA) reduces PLA temperature sensitivity. A pair of I.sup.

Abstract: Circuitry for presetting a bipolar random access memory includes switching transistors, responsive to an applied memory preset signal, for opening the circuit between the memory word lines and their respective current sources, for applying a positive voltage to the bottom word lines, for breaking the circuitry between bit line clamping circuits and their respective power sources, and for grounding the bit line pairs to drain all current from the bit line circuits. The preset circuitry also includes read/write control transistors coupled between each bit line and a V.sub.cc source for steering the set of the memory cells upon removal of the preset signal.

Abstract: A method for forming a predetermined configuration of a film material comprises the steps of forming a layer of a first material on a surface, forming a layer of a second material on the first material wherein the first material has an etch rate greater than that of the second material when the first material and the second material are exposed to a common etchant, etching portions of the second material and underlying portions of the first material to expose portions of the surface, forming a layer of film material on the exposed portions of the surface, forming a layer of film material on the exposed portions of the surface and on the remaining portions of the second material, and removing the remaining portions of the first material such that the overlying second material and the film material thereon is also removed.

Abstract: MOS Control circuitry for incorporation on a microcomputer IC chip for assuring adequate power to maintain the data in an associated static random access memory. A rechargeable battery provides standby power, and the voltage level of the battery is compared with the microcomputer V.sub.cc supply. Whenever V.sub.cc drops below a predetermined level, such as the standby battery voltage level, the circuitry disconnects the V.sub.cc from the memory input power and replaces it with standby battery power. When V.sub.cc is returned to the system, a gate applies a trickle charge to the battery.

Abstract: A semiconductor digital memory such as a charge coupled device is provided with error detection capability. Error logic responsive to a group of data on the input bus generates a first error code which is stored in memory along with the group of data. When the data is retrieved from memory similar error logic generates a second error code. The first and second error codes are compared, and if the codes are identical the data is assumed to be correct. If codes differ then the data is discarded or errors therein are identified and corrected.

Abstract: A technique is disclosed for protecting integrated circuits from alpha particles. A central portion of a radiation resistant insulating substrate upon which electrically conductive leads are disposed is positioned in proximity to the integrated circuit. When the leads are electrically connected to the integrated circuit, the central portion of the substrate is allowed to remain over the integrated circuit to protect the integrated circuit. The insulating substrate typically comprises a polyimide film resistant to alpha particles.

Abstract: A method for fabricating insulating regions in an integrated circuit structure is disclosed in which the insulating regions do not encroach upon the surrounding integrated circuit and in which a substantially planar surface across the top of the insulating material and the substrate is created. The method includes the steps of removing portions of the substrate wherever the insulating regions are to be formed, beginning to deposit insulating material across the substrate and in the openings created, and, while continuing to deposit insulating material simultaneously removing insulating material from generally horizontal surfaces and redepositing it on generally vertical surfaces of the substrate and the openings until a planar surface results.

Abstract: A method and apparatus for exciting the analog input of an analog-to-digital converter and examining the output by means of analysis with histograms to determine the amplitude probability distribution of each digital output value. The amplitude probability density functions corresponding to accurately known excitation signals may then be processed to obtain a description of the transfer characteristic for the analog-to-digital converter to be calibrated. In a particular embodiment, the excitation signals applied to the analog input of the analog-to-digital converter are pairs of signals representing accurately known rising and decaying exponential signals, and particularly exponential signals which are complementary to one another. Histograms of the digital response to the analog excitation signals are then constructed which correspond to amplitude density functions.

Abstract: A video game apparatus for connection to a standard television set and including an electronics-containing console having a plurality of parameter selection buttons and a chute mechanism for receiving a replaceable cartridge-containing supplementary electronic circuitry, and a pair of hand controllers for providing player control inputs to the console electronics. Improved connector apparatus is associated with the chute mechanism to enable electrical connection to be made to a cartridge contained printed circuit board with a minimum of insertion force.

Abstract: A universe of probes is contained within a platen in a spaced-apart, substantially parallel relationship with one another with their tips pointing in the same direction. Each probe is free to move longitudinally between an advanced or test position and a retracted position. The platen nests into a wired personalizer having probe selector posts upstanding therein in a pattern corresponding to the pattern of test points on a circuit board to be tested. These posts serve to push up or advance the probes needed to test a particular type of circuit board. The posts are conductive and each is individually connected to the test system. The circuit board to be tested rests on a special deformable gasket so that its test points are suspended over and aligned with the advanced test probes. When the fixture is evacuated, the circuit board to be tested is drawn downwardly so that the test points on the board make electrical contact with the tips of the advanced probes.

Abstract: A hand held logic probe serially clocks applied data bits into a shift register in response to a user actuated thumb switch. The shift register is coupled to a hexidecimal/octal converter which drives a digital display. The display is reset in response to the user actuating the thumb switch for more than a predetermined time period.

Abstract: A raster scan color display system for a CRT includes a vertical sweep system wherein a parabolic signal repeating at the horizontal sweep rate is multiplied with a vertical sweep signal corresponding to a linear ramp repeating at a vertical deflection rate. The output is differentiated and capacitively coupled to a wideband voltage drive vertical deflection amplifier to provide pin-cushion non-linearity correction.

Abstract: A data latch of the kind having at least two operative modes, a transmitting or transparent mode or condition for transmitting data signals through the latch, and a latching mode or condition for latching and temporary storage by feedback of data signals in the latch. According to the invention there is provided in the data latch a pregate for pregating feedback signals in the latch. The pregate is adapted and coupled to provide positive feedback data signals for reinforcing previously entered data in the latching mode, and gating signals for passing input data in the transmitting mode.