Abstract: In the present invention, a length of elongated single crystal ingot is mounted adjacent its ends and is ground while being rotated to provide a cylindrical shape. While still mounted, the crystal is rotated into a position to be x-rayed for the grinding of a flat thereon with the crystal in a non-rotated state.

Abstract: A transistor logic output device is provided with an active element discharging transistor coupled between the base of the pulldown element transistor and ground or low potential for actively controlling a route to ground or low potential for diverting and discharging the so-called capacitive feedback Miller current generated during the low to high potential transition at the output of the device resulting from base-collector junction capacitance in the pulldown element transistor. The active element discharging transistor is controlled at its base by the potential at the collector of the phase splitter element and is coupled to follow changes in voltage at the phase splitter collector for receiving base drive current during the transition from low to high potential at the device output and when the phase splitter is not conducting.

Abstract: An integrated injection logic device is formed in a pocket of semiconductor material surrounded by oxide isolation, and separated from a substrate by an intervening region of opposite conductivity. The steps for forming the integrated injection logic device include depositing a first material which includes a first conductivity type impurity over a first portion of the epitaxial layer, treating the first material to cause at least some of the first conductivity type impurity to enter the epitaxial layer, and introducing an opposite conductivity type impurity into a second portion of the epitaxial layer. Typically, the first material is polycrystalline silicon doped with p conductivity type impurity.

Abstract: In a transistor logic output device the improvement comprising an active element discharging transistor coupled between the base of the pulldown element transistor and ground or low potential for actively controlling a route to ground or low potential for diverting and discharging so-called capacitive feedback Miller current generated during the low to high voltage transition at the output of the device resulting from base-collector junction capacitance in the pulldown element transistor. The invention includes capacitive coupling means coupled at the base of the active element discharging transistor to follow changes in voltage at the device output and capacitively feed back current during transistion from low to high potential at the device output for driving the base of the discharge transistor thereby providing a low impedance path to ground or low potential at the base of the pulldown element transistor for diverting and discharging capacitive Miller feedback current.

Abstract: A transistor logic tristate output gate or device is provided with active or passive element arrangements coupled between the enable gate on the one hand and the base of the pull down element transistor on the other hand. This coupling affords a low impedance route to ground or low potential from the base of the pull down element when the enable gate is at low potential and the output device is in the high impedance third state. Miller feedback current at the base of the pull down element transistor is thereby diverted to ground. The coupling arrangement affords high impedance to current flow in the opposite direction thereby blocking current flow from the enable gate when the enable gate is at high potential. For active discharge of Miller current three transistors are provided in a double inversion series coupling between the enable gate and pull down element. Alternately a multiple emitter junction transistor is used.

Abstract: A transistor interface circuit for switching analog differential pairs in response to a flip-flop or combinational logic, both output signals of which remain either high or low during switching transitions. This circuitry prevents the differential pair from momentarily saturating or shutting off during the switching transition.

Abstract: A precision motor speed control system employing a phase locked loop in which the inertial mass of the motor, its tachometer and motor driven devices, such as fly wheels, tape transports, etc., perform the functions of the usual low pass filter and voltage control oscillator.

Abstract: Control circuitry for sensing excessive substrate bias voltage in a circuit, such as an LSI N-channel MOS transistor circuit incorporating a substrate bias generator, and for maintaining an optimum bias voltage level by bypassing the excess to ground.

Abstract: A surface oriented lateral bipolar transistor having a base of narrow width is fabricated by using a doped polycrystalline silicon layer as an ion implantation mask when implanting ions for the emitter and base regions. In forming the doped polysilicon mask, a first layer of dopant masking material is formed on the surface of a semiconductor substrate, a second layer of undoped polysilicon is formed over the first layer, and a third layer of dopant masking material is formed over the second layer. Portions of the second and third layers are removed and a dopant is diffused into the exposed edge portion of the second layer. The third layer and the undoped portion of the second layer are then removed thereby leaving only the doped portion of the second layer on the first layer.

Abstract: A process for patterning plasma etchable regions on a semiconductor structure includes the steps of forming a layer of an oxide of aluminum over the surface of the semiconductor structure, forming an overlying layer of plasma etchable material on the layer of oxide, and removing undesired portions of the overlying layer by plasma etching to thereby expose portions of the layer of oxide. In some embodiments of the invention the thereby exposed portions of the layer of oxide are then removed, together with any underlying portions of the first layer, by isotropic etching.

Abstract: A metal-semiconductor field-effect transistor is formed by providing a blanket layer of the same conductivity type as the semiconductor body, with field oxide subsequently being grown, and with a region of opposite conductivity type being formed to extend partially under the field oxide, the initial blanket layer acting as the field implant region of the field-effect transistor.

Abstract: A compact bistable semiconductor memory cell usable in static electronic information storage devices includes a field-effect transistor merged with a bipolar transistor for storing a binary information bit.

Abstract: A semiconductor memory cell comprising first and second bipolar cell transistors cross-coupled by the inverse transistor action of third and fourth bipolar transistors. Each cross-coupling transistor is formed by a single emitter diffusion in an existing common base region of one cell transistor, above a common buried collector region of the same cell transistor. The use of cross-coupling transistors eliminates the need for a direct ohmic connection to the buried layer collector, thereby simplifying layout and reducing memory cell size.

Abstract: A TTL transistor logic tristate output device particularly suitable for common bus applications including transistor and diode means for feedback of a portion of current from any output load and from stray capacitances to drive the pulldown element to greater conduction and accelerate sinking of current from the output to ground during transition at the output from high to low potential, said transistor means also arranged to block paths from the output to ground through the enable gate when the output is in the high impedance third state. Means for blocking current flow from the output through the device to high potential is also described.

Abstract: As a cassette holding wafers in an etchant bath is rotated, nitrogen gas is bubbled through the cassette adjacent the wafers to agitate the wafers, so as to ensure that etchant reaches all edge portions of the wafers.

Abstract: A radiation curable barrier coating having chemical resistance to many solvents, flexibility when cured, selective gloss and excellent abrasion resistance at a coating thickness provided by lithographic printing methods comprises acrylated melamine resin in combination with silica fillers and photoinitiators.

Abstract: Two movable members are selectable positioned to form a passageway for handling dual in-line packages. A wheel, comprising resilient material, and a spreader member are selectable positioned in correspondence with the movable members to engage the leads on either side of the package and vertically straighten them. Lateral straightness of the leads, as well as various other package anomalies, are detected by optical scanning.

Abstract: A charge-splitting device and method include a plurality of charge cells coupled to receive a charge in response to being simultaneously clocked into a charge receiving state by an applied clock signal. The received charge is split into predetermined charge portions among the plurality of charge cells in proportions dependent upon the total number of cells, their relative capacitance and the magnitude and timing of the applied clock signal. The charge portions are again split and selectively summed to obtain highly accurate charge splitting ratios.

Abstract: A display having variable resolution includes a plurality of discrete light emitting elements arranged in an array. Intervals between elements are quantized into a plurality of levels representing information to be displayed. Selected light emitting elements disposed about the levels are energized by a signal having a duty cycle varied in response to displayable information having a magnitude within a particular one of the plurality of levels.

Abstract: A battery-powered hand-held programmable calculator for performing arithmetic, trigonometric and logarithmic functions and displaying the results thereof is provided with the capability of being fully programmable including branching based on data value. Absolute line number addressing is provided. Program line numbers and the key code associated with an executable step are displayed. The top of the programmable memory is configured as a nonexecutable line corresponding to an automatic stop and all other programmable lines are initially programmed upon start up as being an automatic branch to the top of the memory. Key codes representing a plurality of actuated keys corresponding to a branch instruction are merged to require only one program line in memory.