Abstract: A method for patterning a submicrometer substrate element which is smaller than the reproducible resolution accuracy of optical lithography. A series of layers is deposited upon a top layer pattern using standard methods. An edge of the top layer is positioned at or near where the required submicrometer element is to be patterned. A cavity is formed in one of the intermediate layers by removing that intermediate layer in such a fashion that the layer underneath the edge of the top layer is removed. Next, a conformal layer is deposited upon the structure so that the conformal layer fills the cavity. Then the conformal layer is removed and each of the other layers is sequentially removed in such a fashion that only that portion of the conformal layer that occupied the cavity remains, together with any layers that occupy the space underneath the cavity. The remaining layers are the mask for further patterning.

Abstract: A metal oxide semiconductor device having at least one level of polycrystalline silicon interconnects and novel insulation layers for multilevel interconnects. In one embodiment a layer of arsenic doped glass replaces the conventional phosphorus doped glass insulation layer. In other embodiments a layer of arsenic doped glass upon an undoped layer of silicon dioxide provides the insulation layer. Slow diffusing source-drain impurities along with these insulation layers provide minimum lateral source-drain diffusion.

Abstract: A data processing system which contains a read-only memory circuit, an arithmetic circuit, and a control circuit on a single semiconductor chip including a clock generating circuit for supplying system clocks to all of the circuits on the chip and the clock generating circuit is structured such that on the input of an external halt signal, the clock circuits will cease supplying system clocks during a period that provides for information contained within the system on the semiconductor chip.