Abstract: A two player game apparatus includes the inputs for the first and second player, together with display for each player with a common display for providing the game status connected to a single electronic digital processor. The processor system further includes two central processing units where one central processing unit performs the game algorithm for one player and the second central processing unit performs the game algorithm for the second player. Each individual's central processing unit provides individual player status for its player input. Both central processing units provide data for the common display.

Abstract: A timer device includes a multiple bit storage circuit to store a numerical value as a series of binary bits and evaluation circuitry to simultaneously compare the value stored in the storage circuitry with a predetermined value. This invention further includes a counter circuit consisting of a multiple bit storage circuit to store an initial counter value, a counter circuit to receive the initial counter value and to decrement the counter in response to a clock signal and an evaluation circuit to produce an output when the counter value is identical to a circuit defined value.

Abstract: A dynamic metal oxide field effect transistor clocking circuit provides at least one output at a fixed time interval after receiving an input. This clocking circuit includes a first stage which further includes a node connected to the first stage output and circuit capability to charge the node and conditionally discharge the node upon receiving an input. A second stage is connected to the first stage so that the output of the first stage provides the second stage input. The second stage also consists of a node that is charged by circuitry in the second stage and is conditionally discharged upon the occurrence of the input received from the first stage. The second stage includes the capability to block the discharge of the second stage when the first stage discharges without the requirement of a second discharge clock.

Abstract: A circuit that precharges a node and conditionally discharges the node according to the value of an input. This circuit also includes a device to isolate the node from the output line during precharge. This circuit can be fabricated as a positive channel metal oxide field effect transistor and can be structured to perform the logic function of an inverter or an NAND or NOR gate in simple form. This circuit also includes a capacitor that is connected to the precharge node such that additional charge provided by the clocking circuit is used to add charge to the node such that the charge at the node is greater than the charge provided by the circuit power supply alone.

Abstract: An electronic digital processing system implemented on a single MOS/LSI semiconductor chip including a ROM for storing instruction codes, a RAM for storing data, an arithmetic logic unit for performing operations on data under control of microinstructions or commands, control circuitry for generating commands in response to the instruction codes in a plurality of central processing units. The fetching of instructions from the ROM, the accessing of data from the RAM, the operation of the arithmetic unit are controlled by the central processing units which share the same data paths that couple the central processing units to the ROM, RAM, arithmetic unit and control circuitry.

Abstract: A memory cell includes a gated capacitor connected to a first node and also connected to a refresh line. The memory cell further includes a transistor that is also connected to the first node and to a second node with the gate terminal being connected to a second refresh line. The second node is connected to the bit line used to access the bit information contained in the cell. A second transistor is included that has one side connected to a power line, the second side connected to the second node and the gate terminal connected to the first node. A first refresh signal is provided on the refresh line connected to the gated capacitor and a second refresh signal is provided to the gate of the first transistor. The second refresh signal is of a voltage magnitude greater than the voltage provided on the power line and the second refresh signal is also provided at a time during which the first refresh signal is absent.

Abstract: A read-only memory includes several branches of transistors which are connected to address decode circuitry together with transistors to address each of the branches where these addressing transistors are also connected to address decode circuits. Each of the addressed branches are capable of conditionally discharging a precharged node dependent upon the stored data in the transistor branches.

Abstract: A read-only memory includes an array of rows and columns of memory cells with row lines and column lines associated with the array. The row lines are partitioned into groups that provide bits of a word on a number of output lines. Each group consists of an output line and a first voltage line with a plurality of row lines in between. A row selector is provided that receives an address signal for selecting a particular row in each group and connects a row line on one side of the selected row to the first voltage line and connects the row line on the other side of the row to the output line. A row precharge circuit is provided for precharging the row lines prior to the connection of a row line to an output line. Also provided is a column select circuit for receiving an address signal for connecting a particular column line to a second voltage line and for connecting one or more of the remaining column lines to one of the first voltage lines in order to reduce coupling.

Abstract: A quadruply time-multiplexed bus for digital processor systems. The quadruply time-multiplexed information bus is interfaced to a processor and an external memory to transfer addresses, data and program instructions between the processor and the external memory. The interface at the external memory includes the capability to store the addresses of extended bus or instructions being accessed. These stored addresses may be modified from the processor by the processor transmitting new addresses over the information bus or by having the processor activate selected control signals in the information bus interface which causes the stored address to be modified in response to the control signals. This feature is useful to read a new instruction from external memory without the requirement of a new transmission of program instruction address every time a new instruction is fetched by the processor.

Abstract: A sampling switch circuit is provided for an analog to digital converter that provides for the scaling of two switches connected to the converter comparator. The comparator receives two input voltages which are switched to reference voltages. To correct any offset voltage resulting from a mismatch between the switch circuitry, this invention provides for one switch to be attached to a capacitor while the second switch is attached to the capacitive array that digitizes the analog input. These two switches are proportionally fabricated according to the size of their respective capacitive load in order to reduce any voltage difference resulting from the capacitive coupling internal to the switches. The switching circuitry also implements a sequence of switching to correct the offset error from capacitive coupling.

Abstract: A digital synchronizer includes a latch connected to a level sensitive circuit. The latch is constructed to provide a rapid transition between logic "0" and logic "1". In addition, the latch is periodically cleared. The level sensitive circuit provides a propagation barrier to any metastable state that may be present in the latch. However, the level sensitive circuit is also constructed for rapid transition from logic "0" to logic "1" when such a state occurs within the latch. An additional latch is connected in a further embodiment to provide additional reliability of the synchronizer circuit. The second latch is a two inverter latch with refresh for 3/4 of a machine cycle to allow any transients conditions within the latch to dampen out.

Abstract: An analog to digital converter is provided which includes a binary weighted capacitor array connected with a series of resistors structured as an array. The converter provides for charge correction to compensate for any capacitance deviation in the capacitor array. The converter includes a charge redistribution sequence under the control of a microcomputer to determine the digital value of the analog input using the resistor array to determine the least significant bit positions of the analog input. This same resistor array is also used to correct for capacitor value deviations in the binary weighted capacitor array.

Abstract: Error correction circuitry for an analog to digital converter is disclosed which provides for the correction of charge in a charge redistribution converter architecture. This conversion technique as implemented requires that a binary weighted capacitor array be present where the capacitors are accurately binarily weighted in decreasing value. The charge correction circuitry allows for the correction of any deviations of binary weighted capacitance value by adding or subtracting charge from the capacitor array. This is accomplished by the use of a resistor array connected to a capacitor that is equal in capacitance to the smallest capacitor in the capacitor array. The converter includes a microcomputer which determines the charge error for each of the individual capacitors together with the total charge error for the capacitive array coupling with the comparitor.

Abstract: An electronic apparatus with processing capability dedicated to the display function. This apparatus includes a keyboard for inputting data into the processor system and a display for presentation of the output data from the processor system. The electronic digital processor system includes a memory, an arithmetic and logic unit and two central processing units that operate independently and simultaneously. The keyboard input is connected to one central processing unit and the display is connected to the second central processing unit. The algorithm in the first central processing unit is dedicated to obtaining inputs from the keyboard and performing certain operations defined by the function of the apparatus. The algorithm contained in the second central processing unit is dedicated to the display of output data contained in a RAM in the digital processor system. Since both central processing units operate simultaneously and independently, they both use the same locations in RAM.

Abstract: An electronic digital processor system including a plurality of processing units with dedicated input port and output port for each of the processing units and an output port that is shared by the processing units. The digital processor system also includes a ROM for the storage of commands, a RAM for the storage of data, an arithmetic and logic unit for performing operations on the data, two independent and simultaneously operable processing units for executing these commands on the data and the control circuit for providing for simultaneous execution of commands in both processing units.

Abstract: A high-frequency channel selector for a television receiver including at least one fixed filter having a predetermined passband, and a high-frequency mixer. The antenna for the television receiver receives radiated electromagnetic signals including, for example, a plurality of television channels. The fixed filter has an input coupled to the antenna and filters one fixed frequency spectrum of television channels from the received signals. The mixer has inputs coupled to simultaneously receive the fixed frequency spectrum of channels and mixing signals of a high selectable frequency. The high selectable frequency shifts selectable channels of the spectrum to high intermediate frequency substantially greater than 45 MHz.

Abstract: A method and apparatus is disclosed which corrects for errors produced in data acquisition systems. Disclosed is a method and circuit for correcting errors, such as mismatch between binary weighted capacitors and offset, in a charge redistribution, weighted capacitor array analog-to-digital converter. A self-calibrating, self-correcting circuit is comprised of a second binary array of capacitors which adds to the regular charge redistribution capacitor array an error correcting signal to compensate for the mismatch. This error correcting signal is then stored and the other error correcting signals for other capacitors in the regular capacitor array are determined and subsequently stored for later correction of other capacitance mismatch.

Abstract: A method for fabricating a semiconductor device of relatively small scale. A conductivity layer is deposited on a substrate of a polarity. Regions of opposite polarity are partially formed on either side of the conductor layer. Vertical layers are formed to partially cover the regions of opposite polarity and are located adjacent to the conductor layer. Extensions of the regions of opposite polarity are formed such that a portion of the extension is defined by the location of the vertical layers.

Abstract: A method for fabricating a metal oxide semiconductor device having at least one level of polycrystalline silicon interconnects and novel insulation layers for multilevel interconnects. In one embodiment, the fabrication processing includes forming a layer of arsenic doped glass as a multilevel interconnect system insulating layer. In another embodiment, the method includes the formation of a multilevel interconnect system insulating layer which includes the formation of a layer of undoped silicon dioxide as a barrier layer and then forming a layer of arsenic doped glass upon the undoped layer.