Abstract: In a data processing system, particularly one implemented by a microprocessor, apparatus is provided for bypassing the main parallel information bus between the processor and main storage unit by a serial information bus for testing purposes. Serial test information is applied through the serial information bus to a storage control unit which interfaces the processor and storage unit. The control includes circuitry for converting the information from the serial bus into the parallel format of the data which is provided from the processor along the main parallel bus. The test information applied has the same commands and address structure as the information output from the central processor. As a result, when the serial test information is converted to parallel format, by the apparatus, it will be indistinguishable from parallel data applied directly from the processor along the parallel bus.

Abstract: An audio editor comprising circuitry for converting a received audio sound recording into digital data blocks, where each data block represents a corresponding portion of the sound recording during a predetermined time interval. Also included is circuitry for storing the data blocks as a consecutive sequence representing the sound recording. A display circuit is provided for display the data blocks as a timed based graphical representation to a user. Also provided is a method of displaying the sound recording including the steps of (1) converting the received sound recording into digital data blocks, (2) displaying an axis representing time, (3) displaying a graphical representation of the digital data adjacent to the time axis corresponding to the relative time position of a corresponding sound recording portion in that time period, and (4) displaying at least one user locatable mark on the time axis representing a time point of the sound recording.

Abstract: An apparatus for producing machine executable object code, a program listing and a listing of design documentation from a source code program consisting of a plurality of statements of implementation code including keywords and a plurality of statements of design documentation code wherein the design documentation code includes words corresponding to the keywords of the implementation code. The apparatus includes a processor for reading the source code program, a compiler for producing the machine executable object code from the implementation code, and the program listing. Furthermore, the apparatus includes an extractor that produces the design documentation by listing all of the design documentation code with the corresponding keywords in the order of appearance in the source program.

Abstract: In a graphics display system a counter for performing either a line drawing algorithm or a bit block transfer algorithm where the counter is performing the bit block transfer algorithm includes a first counter circuit counting from a first initial state to a first predetermined value and a second counter circuit counting from a second initial state to a second predetermined value. The second counter counts in response to the first counter reacing to its predetermined value. In support of a line drawing algorithm, the counter circuit reconfigures itself to provide a first counter to count from its first initial state to the first predetermined value and a second counter to compute a parameter value and to conditionally count from a second initial value to a second predetermined value in response to the value of this parameter. These counters are connected to an addressing circuit to increment the addresses in performance of the algorithms.

Abstract: A communication bit pattern detection circuit that provides an output signal upon the occurrence of one of several predefined bit patterns for a series of a specified number of bits for a multiple of input signals where each input signal is a continuous stream of serial bit data. The communication bit pattern detection circuit includes a detection stage having combinational logic connected to receive the input signals and providing the logically combined bits to latches of a shift register. The number of latches in the shift register is less than the specified number of bits for the predefined bit patterns. The output of these latches are provided to a logic stage that includes additional combinational logic that provides a nondetection signal. This nondetection signal is provided to indicate that the bits received are not part of any of the predefined bit patterns. The nondetection signal is input to reset a counter.

Abstract: A data processing system including several devices connected to an asynchronous communications bus for communications between these devices. The communications bus includes a protocol that requires only a single device to regulate communication between devices at any one time. This regulating device is termed the bus master and the remaining devices are termed slaves. This protocol provides the capability for a slave device to indicate to the bus master that a new bus master is to be designated for a temporary communication. This communication with a different bus master then occurs during the communication of the designated bus master.

Abstract: A graphics display system including a circuit that receives graphics information to be displayed and a memory that stores the graphics information in a memory array that includes a portion that directly corresponds to the image area for display. The memory provides a single access operation to the array during a single memory cycle. Circuitry is provided that is connected to the receiving means and to the memory that provides graphics information to an N by M portion of the memory array during a single memory cycle (wherein N and M are integers each greater than one). A display is connected to the memory that displays the graphics information contained in the image area array portion of the memory. The graphics display system further includes the capability to provide a patterned line intersection where the continuity of the line pattern is maintained along the intersection of the lines.

Abstract: A microprogrammed parallel processor including a plurality of subprocessors operates under the control of microinstructions. Each microinstruction contains a plurality of micro-operations each of which requires one or more subprocessors for execution. All micro-operations for which required subprocessors are available are immediately carried out. Any remaining micro-operations within a microinstruction which are not executed due to lack of subprocessor availability are recycled. These remaining micro-operations are executed in subsequent cycles as a required subprocessor becomes available. The entire microinstruction is not recycled but only those portions of it, i.e., the unexecuted micro-operations, are recycled and executed in a subsequent cycle. The microinstruction being executed is stored in a latch until all micro-operations within the microinstruction are executed. At that time, the next microinstruction is fetched into the latch.

Abstract: A method and apparatus expands the capability of an instruction prefetch buffer. The method and apparatus enables the instruction prefetch buffer to distinguish between old prefetches that occurred before a branch in an instruction stream and new prefetches which occurred after the branch in the instruction stream. A control tag is generated each time a request for an instruction is sent to a storage. The returning instruction has appended thereto the original control tag which is then compared to the current value of control tag in the instruction prefetch buffer. If the two values match, then this is an indication that a branch has not occurred and the instruction is still required. However, if the two values of the control tag are not equal, then this is an indication that a branch in the instruction stream has occurred and that the instruction being sent from storage to the buffer is no longer required.

Abstract: A programmable logic array having a plurality of electrically isolated input lines connected to an input circuit for providing an input signal to one of the plurality of input lines. Also included are a plurality of electrically isolated output lines positioned relative to the input lines to form an array having a plurality of non-conductive intersections. A plurality of programmable circuits, each positioned at a selected one of the intersections and interconnecting an adjacent input line, an adjacent output line and one of two output potentials that define one of two output states are provided. The programmable circuit is further connected to the input line such that when an input signal is received on the input line, the selected output potential representing one of the two output states is provided on the output line.

Abstract: A memory circuit including a bit addressable binary data memory in which the data is stored in a plurality of dimensional directions and a circuit for accessing a group of the data in the memory in at least two of the dimensional directions and for moving the data to a different dimensional location while maintaining the data within the group. Also provided is a means for accessing the data by incrementally or decrementally addressing the data in at least one of the directions. The accessing circuitry is further used to perform bit block transfers of data within the memory. The accessing circuit also provides for horizontal or vertical access during a read operation while orthogonally rotating the data by 90 degrees during a following write operation.

Abstract: A method and apparatus of providing a visual representation of a curve image wherein curve image data is provided by a B-Spline equation computed with a forward difference technique using scaled integer variables. The method provides for the scaling of the initial base matrix computation of the geometry vector coefficients followed by the computation of the forward difference interval coefficients using integer arithmetic. The curve coordinate values for each interval are computed from the forward difference interval coefficient integers descaled by the scaling parameter. By employing integer arithmetic in a divide approximation technique, the use of floating point arithmetic is avoided. The apparatus for producing the visual representation of the curve image includes a computational section that provides for pipelined computations of the forward difference interval coefficients to provide high-speed curve coordinate value computation.

Abstract: An addressing circuit for providing character addresses to refresh a plurality of panels arranged to display a single image and including a circuit for providing a character counter across character line and a circuit for providing a character line count for each panel. The character count across the character line and the character line count are combined in another circuit to provide an address for each character successively along a panel scan line alternating between each respective scan line of the panels. In this manner, each scan line of the panels may be addressed in an alternating fashion to provide the required refresh signal to maintain the image on the display.

Abstract: A system to display an image including a first memory for storing picture data representing the image attribute data to qualify the picture data. The attribute data includes embedded synchronization data. The system further includes a circuit that produces the image by scanning the picture data qualified by the attribute data onto to a display in accordance with the synchronization data. This invention further provides for storing the synchronization data within the attribute data enabling the synchronization data to be programmable but only requiring update of the synchronization data when the synchronization data is to be changed. The memory includes two buffers wherein one buffer is loaded with attribute and synchronization data while the other buffer is being read. After the other buffer is read, the buffers are toggled such so that the loaded buffer is read to provide the attribute and synchronization data while the previously read buffer is loaded with new attribute and synchronization data.

Abstract: A memory system for providing a contiguous address space and including several memory modules each having circuitry to provide information of their respective memory module capacity to a control circuit. The control circuit allocates a start address to the first memory module and allocates start addresses to the remaining memory modules in accordance with previously allocated start addresses and the memory capacities of the memories that have received their respected start addresses. In one embodiment, the control circuit includes a series of adders each connected to a memory module to receive memory capacity data. The adders are connected in series to compute the start addresses in a daisy chain fashion.

Abstract: An apparatus directs storage requests from a processor through a storage controller to storage. The storage controller contains address comparators which are uninitialized, i.e., they contain no address identifiers. As a result, logic within the storage controller is used to direct these storage requests until the address comparators become initialized. The storage controller directs the first and all subsequent storage requests to a read only storage if the first storage request is for a load, or read, operation. Conversely, the storage controller directs the first and all subsequent storage requests to a random access memory if the first storage request contains a store, or write, operation. An initialization program contained in an I/O device is loaded into the random access memory at the time the first storage request containing a store operation is made.