Abstract: A word processing system is provided with an interactive display terminal for displaying by character generation a data stream representative of alphanumeric characters to be printed on a document together with means for printing the characters on the document. The processing system integrates into the data stream, data representative of graphics and converts such integrated graphic data into graphic display characters whereby the graphics may also be displayed through character generation. When printing of the graphics and alphanumeric information to produce documents is required, the data in the data stream representative of alphanumeric characters is applied to the printing means resulting in the printing of the characters and the data in the data stream representative of the graphics is applied to apparatus for producing the graphics such as a plotter to produce the graphic content of the document.

Abstract: A cursor generation circuit for an image display system that includes a storing circuit for storing image data. The storing circuit includes a first port to provide access to the image data to the display system and a second port to provide access to the image data to a display device for displaying the image data. A combining circuit is further provided to combine the image data with cursor data in the storing circuit when the storing circuit is being accessed by the display device. However, the combining circuit removes the cursor data from the image data when the image data is being accessed by the display system through the first port.

Abstract: A data processing system having a main processing unit, a memory subsystem, and a co-processor selectively connectable to said memory subsystem through an Input/Output Channel Controller which includes a control means for arbitrating access to the I/O Bus among the co-processor and the other I/O devices connected to the Bus. Since the co-processor runs programs stored in the memory subsystem, there is a tendency for the co-processor to monopolize the bus with instruction fetch cycles, thereby excluding other I/O devices from access to the bus. The control means for arbitrating responds to requests on the basis of a linear priority scheme in which the co-processor has the lowest priority. Each device, except the co-processor, is permitted to keep control of the bus until it voluntarily relinquishes it. The co-processor, on the other hand, relinquishes control of the bus in response to a request for access by any higher operator.

Abstract: An improvement in a bus converter that provides a bus to bus address translation function permitting access from an I/O device connected on the I/O bus to a system bus and system memory, where the bus converter includes a circuit connected to the I/O bus to partition I/O addresses received from the I/O bus into a lower order field and a high order field and connected to a circuit to receive DMA ID's from the I/O bus to combine this DMA ID with the high order field to form a first combined address. The first combined address is input to a memory which provides corresponding control field and prefix field data. An address formatter is further included that is connected to receive the control field and prefix field data from the memory and further connected to receive the low order address field. The address formatter forms a second combined address from the prefix field, control field and lower order address field. This second combined address is then provided to a system bus to permit access to the system bus.

Abstract: A frequency multiplier circuit including a circuit element to receive an input signal having a first frequency which is provided to a phase shifting circuit element to provide an intermediate signal resembling the input signal except shifted in phase. This intermediate signal is provided to a logic element which combines the intermediate frequency with the input signal to produce an output signal having a second frequency which is a multiple of the first frequency.

Abstract: A word or text processing system has a bidirectional printer with formatting capability. A line of text is printed in one direction, and the printer is backspaced to form complex characters by adding overstrikes, such as underlining or accent marks. The formatting unit includes a storage mechanism for storing encoded space images, including variable width spaces, in a first scan pass. Space images overlapped by a backspace are deleted from the storage mechanism during the scan pass, and the number of spaces backspaced over is subtracted from the total count of expandable spaces available for justification. Upon detecting a space in the input data during the format pass, the system examines the space storage mechanism to determine if the image of the space is encoded therein. A space is expanded for line justification only if the space is encoded in the space storage mechanism.

Abstract: A plurality of controllers are connected to a common bus in turn connected to a central processor. Each of the controllers respectively serves as an interface between the central processor and at least one storage unit for input/output device. In order for the controllers to distinguish between addresses, the addresses sent from the central processor contain identifier segments indicative of the controller to which the address is being sent. Controllers in turn contain programmable comparison means for comparing the identifier segments in addresses to a stored controller identifier indicative of the controller. Because the comparison means are programmable, controller identifiers have to be set up each time the system is turned on.

Abstract: A virtual memory address translation mechanism is provided for converting virtual memory addresses provided by a CPU into real memory addresses within page frames in a large hierachial memory wherein the real memory space is substantially smaller than the scope of the virtual memory. The conversion or translation mechanism includes a combined table in the memory which includes a first list covering the respective virtual address of each memory address (Inverted Page Table or IPT) and a second list connecting each of a plurality of hashed addresses with a predetermined initial virtual address of a linked group of virtual addresses, each of which when hashed produces the connected hashed address (Hashed Addressed Table, HAT). The system also has means for hashing a selected virtual address to produce a hashed address.

Abstract: A communication system is provided in which one data transmitting display terminal has the capability of transmitting a data stream in coded form to at least one data receiving terminal over a communication linkage. This data transmitting terminal further includes the capability of displaying, when necessary, the stream of coded data directly on its display so that if there is a transmission problem, the coded data itself can be analyzed in diagnosing the problem.The present communications system has the further capability of diagnosing data streams at remote display terminals. For example, if one transmitting terminal is communicating with a receiving terminal and a problem arises between the two terminals, the system provides the capability of the transmitting terminal sending the data stream to another receiving terminal remote from the first two terminals.

Abstract: A plurality of data processor units are connected to a common bus which is connected to first and second interleaved storage units. The system is a synchronous one in which timing means establish a series of information transfer intervals. One or more of the processor units contain apparatus for selectively commencing an address transfer on the bus to one of the storage units during a transfer interval; the storage transaction initiated by the address transfer will require more than the one transfer interval to complete. One or more of the processors have means for monitoring the bus in order to determine whether an address on the bus has been transferred to the first or the second storage unit during a particular transfer interval. The address transfer apparatus further includes apparatus responsive to the monitoring apparatus for selectively transferring the next subsequent address to the other of said storage units to thus achieve alternating interleaving between storage units.

Abstract: The present invention is directed to a conventional data processing system having a CPU and at least one external unit such as the main storage unit acquiring data from or providing data to the CPU and I/O bus for the transfer of data between the CPU and the external unit. The apparatus of the present invention provides for transfers to and from this external unit, e.g., main storage being overlapped with a register to register data transfer routinely carried out in the CPU to implement various CPU operations and computation functions. The CPU includes apparatus for transferring data to or from said external unit over the I/O bus during synchronized time cycles. The CPU also includes local storage apparatus which comprise a plurality of registers as well as expedients for transferring data from register to register. Control apparatus controls the register to register data transfer so that such transfers are conducted during time cycles coincident with the transfer of data to or from the external storage unit.

Abstract: An impact printing system which is particularly suitable for word processing is provided with the capability of effecting mid-line pitch changes. The impact printer system which is particularly compatible with interactive display terminals in word processing system has means for receiving a selected one of a plurality of type or character font elements. The pitch of character font elements are different from each other. The printing system includes means for selectively impacting selected characters from selected fonts along lines in a document. The system further includes control apparatus for controlling and determining the selection of font elements to be used and in the case of printing with a particular font element, the characters to be printed in respective positions along the lines of the document to provide the desired document format. The control apparatus includes apparatus for controlling the printing with at least two different font elements having different pitch along a single line.

Abstract: A low power oscillator circuit including a latch connected to two loops. Each loop includes dynamic inverters and static inverters connected in cascade. The loops are connected to the latch such that the output of the final stage is an input to the latch. An initialization circuit is included on one loop to initiate oscillation. Storage capacitors are included in the loops to provide an oscillator output voltage that is greater than the oscillator power supply voltage.

Abstract: A digital synchronizer circuit including an input to receive an asynchronous level and a second input to receive an ansynchronous pulse. Both inputs are connected to the synchronizer input circuitry which will provide a level output for either type of input signal. This circuitry is connected to the remainder of the digital synchronizer which includes a latch connected to the level input and a level sensitive circuit connected to the output of the latch. The latch is constructed to provide a rapid transition between a logic "0" and "1". In addition, the latch is periodically cleared. The level sensitive circuit provides a propagation barrier to any metastable state that may be present in the latch. However, the level sensitive circuit is also constructed for rapid transition from a logic "0" to a logic "1" when such a state occurs within the latch. An additional latch is connected in a further embodiment to provide additional reliability of the synchronizer circuit.

Abstract: An electrically programmable read-only memory including a memory array of several bits capable of storing binary data connected to an address circuit for accepting a plurality of bits that designate a selected set of the memory array bits and further connected to a data latch to store data to be programmed in a selected set of memory bits. Further provided is a high voltage circuit for providing a high voltage to the selected set of bits according to the data in the data latch and for programming the data in the selected set of memory array bits. Further provided is an output circuit to provide a precharge signal to the memory array bits and to output data programmed in a selected set of memory array bits designated by the address circuit.

Abstract: A digital clock generator circuit including a series of inverters connected in cascade with the output of the final stage connected to the input of the first stage in a ring counter fashion. Each inverter includes a first circuit to precharge a node, a second circuit to discharge a node upon occurrence of a selected input signal and a third circuit connected to isolate the node from the circuitry output during the precharge interval. The output of the counter is the output of the final stage. The inverter circuits allow for a low power digital counter by allowing a P-MOS or N-MOS fabrication of devices that do not require continuous power.

Abstract: A digital processing system includes an external memory for the storage of program instructions for use with a separate processor that internally contains a memory for temporary storage, an arithmetic and logic means, a register set, control and timing circuitry, and two sets of data paths. The first set of data paths provide access to the external memory for transfer of instructions from the external memory to the processing unit. The second set of data paths provide for the internal routing of instructions data and addresses within the processor unit itself. The data structure for the first set of data paths is different than that for the second set of data paths, providing for an external data structure that is different than the internal data structure of the processor.

Abstract: An electronic digital dual processor system including an interface to an external memory in addition to an internal memory. The dual processor architecture includes dual independent and simultaneously operable registers for the temporary storage of data from an arithmetic and logic unit and for memory addressing. The internal memory includes a ROM for storing instructions and a RAM for storing data. The internal memory is also used to store instructions. Control and timing circuitry is included for the generation of microinstructions for the instructions stored in the memory. The control and timing circuitry provide for the simultaneous and independent execution of the microinstructions involving the dual register sets.

Abstract: A digital processing system includes a memory for the storage of both data and instructions of M binary digit widths a N (N.noteq.M) binary digit parallel arithmetic and logic unit and self-test circuitry connected to the memory and connected to the arithmetic and logic unit for summing the numeric value of the contents of the memory into a set of sums that are N binary digit width and for comparing these sums with corresponding checksum constants to determine the integrity of the instructions stored in memory and the integrity of the arithmetic and logic unit operation.

Abstract: A two player game apparatus includes the inputs for the first and second player, together with display for each player with a common display for providing the game status connected to a single electronic digital processor. The processor system further includes two central processing units where one central processing unit performs the game algorithm for one player and the second central processing unit performs the game algorithm for the second player. Each individual's central processing unit provides individual player status for its player input. Both central processing units provide data for the common display.