Abstract: To rapidly draw straight lines and circular arcs of width 1 on a raster scan graphic display by determining whether or not the point, the X coordinate of which is incremented by 1 relative to the current point, and the point, the Y coordinate of which is incremented by 1 relative to the current point, are between the outlines f1 and f2 defining a straight line of width 1. If the point, the x coordinate of which is incremented by 1, is between the outlines f1 and f2, it is plotted and selected as the next pixel. If this is not the case, and the point, the y coordinate of which is incremented by 1, is between the outlines f1 and f2, it is plotted and selected as the next point. If neither point is between the outlines f1 and f2, the point, the x and y coordinates of which are incremented by 1, is plotted and selected as the next pixel.

Abstract: A method of shrinking an image stored in a first array including the steps of separating the first array into a plurality of rows, each row having a first plurality of data elements, each element having a value, and separately shrinking each row from a first plurality of data elements in the first array to a second plurality of data elements in a second array including the steps of correlating each of the second plurality of data elements to at least one of the first plurality of data elements, and calculating the value of each of the second plurality of data elements from the values of correlated data elements.

Abstract: A data processing system including a circuit for storing a plurality of instructions in a sequence together with a circuit for fetching a plurality of instructions. A circuit is provided for dispatching a plurality of the instructions to one or more processors for execution during a single computation cycle. A control circuit is connected to the dispatching circuit to delay the dispatching of an instruction. when the instruction has an execution result that is dependent upon a previous instruction execution that will set at least one bit in a condition register. The delayed instruction is delayed until that condition register has been accordingly set.

Abstract: In a multitasking data processing system for executing a plurality of independent processes and including at least one peripheral device, a peripheral manager is provided that includes the capability for providing a first set of data structures where these data structures are dependent upon the peripheral device, a second data structure where the second data structures are dependent upon each of the processes in the data processing system, and the capability for providing a process access to the peripheral device by combining the accesses to the first data structure and the second data structure, as appropriate.

Abstract: A data processing system including a processor that issues communications commands on a first communications channel and a peripheral device that is connected to the first communications channel and to a second communications channel that operates asynchronously relative to the first communications channel. The peripheral device performs communications operations specified from the commands from the processor and further responds to communications over the second communications channel. The peripheral device includes a controller that provides a status word to the processor in response to the command issued to the peripheral device. The status word indicates the status condition of the peripheral device at the time when the peripheral device initiates the operation specified by the issued command.

Abstract: A communications network including several ports where each port is connected to at least one data processing system element. The ports are interconnected by an information bus. Additionally, the ports are connected to a matrix switch that has the capability of providing a direct communications channel between any two of the ports. Each port includes control circuitry for communicating with other ports over the bus and through the bus, regulating the matrix switch in order for the matrix switch to provide the direct communication channels between two ports.

Abstract: A cache for use with input/output devices attached to an input/output bus. Requests for access to system memory by an input/output device pass through the cache. Access authority is checked to determine whether an input/output device is authorized to access that particular page. If it is not, access is denied. Each input/output device has access to a portion of the cache, so that activity by one device will not interfere with activity by another.

Abstract: A multitasking data processing system for executing a plurality of processes is provided that includes a single peripheral device addressable through two ports. A peripheral device manager is provided that includes the capability of (1) allowing access to only a single process for accessing the peripheral device and (2) the capability to provide access to a first process while simultaneously and concurrently providing access to a second process to a second port.

Abstract: A data processing system is provided that includes a plurality of execution units each including independent circuits for storing and executing instructions. A circuit is also included for providing instructions from a sequence of instructions to the execution units where each instruction is provided to only one of the execution units. The system includes a circuit for detecting when an instruction in a first execution unit must complete execution prior to execution of an instruction in a second execution unit to produce correct results. A circuit is further included, responsive to the circuit for detecting, for delaying executing the instruction in the second execution unit until the instruction in the first execution unit has completed execution.

Abstract: An all events trace gatherer for a logic simulation machine is disclosed. The all events trace gatherer generates an all events trace (AET) which is a record of what has happened to all or a subset of the facilities by monitoring a simulation bus on which the logic simulation machine put a calculated result during the simulation thereon. The AET gatherer allows an AET to be gathered without slowing the simulation. The AET gatherer is an auxiliary processor that is connected to the simulation bus in the logic simulation machine in parallel with simulation processors of the machine.

Abstract: A data processing system that executes a process and further includes the capability to provide an interrupt signal upon the occurrence of a predetermined event. An interrupt manager is provided that includes the capability to receive the interrupt signal and provide data indicative of the occurrence of the interrupt signal. Further the interrupt manager includes the capability to evaluate this data according to a predetermined criteria to determine if an event signal should be provided to a process. Lastly, a capability for providing the event signal only when initiated by the evaluating process is provided.

Abstract: A data processing system that includes several ongoing processes that provide input words to a buffer of an independently executing processor, a buffer manager that controls the process access to the buffer and controls the words input by the processes to the buffer that includes an apparatus for regulating the number of words from an executing first process for loading into the buffer, an apparatus for loading the number of words, an apparatus for loading a synchronization word when a second process is to be executed and an apparatus for halting the loading of the first process words and providing for loading of the second process words when the synchronization word is accessed by the independently executing processor.

Abstract: A method for performing floating point division is provided for producing a quotient having a mantissa of n bits. The method consists of the steps of accessing an initial guess of a reciprocal of the divisor from a table of divisor reciprocals, computing an initial estimate the quotient in a corresponding estimate from the initial estimate of the reciprocal, increasing the precision of the mantissa of the reciprocal estimate, quotient estimate, and remainder estimate by computing an error parameter and iteratively computing a current reciprocal estimate, a current quotient estimate and a current remainder estimate from the error parameter and the latest reciprocal estimate, quotient estimate and remainder estimates. Also, the step of increasing the precision is repeated until the quotient estimate and reciprocal estimate exceed n bits. Lastly, the final quotient is computed from the last current quotient estimate plus the last current reciprocal estimate times the last current remainder estimate.

Abstract: A data processing system for executing a sequence of instructions. The data processing system includes several processors each for executing instructions. Also included is a dispatching apparatus for dispatching each of the instructions to one of the processors. Control circuitry is included for directing the concurrent execution of the dispatched instructions in the processors irrespective of the location of the instructions in the sequence. The control circuitry includes the capability to receive an instruction interrupt signal. The control circuitry then determines which instruction generated the instruction interrupt. Upon this determination, the control circuitry resets the processors and the dispatching apparatus to the state that existed when the instruction that generated the instruction interrupt was earlier executed in order to re-execute the instruction that caused the interrupt signal in accordance with its location in the instruction sequence.

Abstract: A data processing system that includes a plurality of processors with at least a portion of this plurality of processors each individually connected to a cache memory for storing data for that processor. Each cache memory includes a cache controller that is connected to a bus. Each controller includes a circuit for independently storing a data coherency procedure indicator indicating that the controller will perform one of two or more data coherency procedures. According to one procedure, when data is updated in a cache memory, corresponding data is updated in another cache that stores the corresponding data. In a second data coherency procedure, when data is updated in one cache, the corresponding data stored in another cache is invalidated. The individual and independent storing of the coherency procedure indicator enables each cache to perform either one or the other data coherency procedure without interfering with the data coherency procedures performed by other caches in the data processing system.

Abstract: In a data processing system configured to transfer data in words and an apparatus is provided for manipulating, in response to a single manipulation instruction, the contiguous variable length sequence of data stored in bytes including an instruction decoder for decoding a single manipulation instruction, a memory for storing data in words where each but word includes a plurality of bytes, a circuit responsive to the command signal from the instruction decoder to access a contiguous sequence of the bytes from the memory wherein the first byte of the sequence is not stored on a word boundary, and providing the byte sequence to a plurality of data processing registers wherein the first byte of the sequence is aligned with the first registered boundary. Additionally the apparatus includes the capability to provide the contiguous sequence to memory wherein the first byte of the sequence is not stored on a word boundary.

Abstract: A processor for performing floating point arithmetic operations is provided that includes a circuit that performs a first floating point arithmetic operation on a set of operands in a first cycle and and a second floating point arithmetic operation on an operand and a result of the first floating point arithmetic operation during a second cycle. A control circuit is provided for, in a third cycle, transferring a result of the second floating operation to the first floating point circuit for a first floating point operation in a next successive cycle while rounding the result of the second floating point operation.

Abstract: An arithmetic circuit for performing an integer power operation having a first register that is initially stored with integer power data, a second register stored with base data and a multiplier for multiplying the second register contents with a third register. A control circuit is provided for iteratively shifting the first register and for each iteration (1) selectively multiplying, according to data shifted from said first register, the second register data by the third register data and storing the results in the third register, and (2) multiplying the second register data by itself and storing the results back into the second register. These iterative steps are continued until the remaining data in the first register indicates that the arithmetic operation is complete, whereupon a completion signal is provided.

Abstract: A communication system for providing a communication path between two of a plurality of devices. A first port is provided that is connected to at least one device. A second port is provided connected to a second device. A switch is provided connecting the two ports for communications connection between the ports in response to commands form the devices to each other. The switch includes the capability to monitor communications between the devices and to determine when a change is to be made in the communications path and then to make the change accordingly.