Abstract: The present invention relates an absorptive high temperature desorber for mechanically narrowing the width of the combustion area, and an absorption chiller-heater using the absorptive high temperature desorber. The high temperature desorber comprises a plurality of combustion chambers, a group of liquid ducts arranged in the perpendicular direction in the combustion chambers, and the distribution chambers independently supplying a mixing gas to the plurality of combustion chambers. Therefore, the high temperature desorber can form flame independently and variably in the combustion chamber, and has a mechanically small width.

Abstract: A switchable amplifier circuit having a current mirror. The mirror includes: a first current source for producing a reference current; an output transistor having an input electrode and an output electrode; and a current gain device connected between an output of the first current source and the input electrode of the output transistor. A bias current is produced through the output electrode of the output transistor, such bias current being a function of the reference current produced by the first current source. A second current source has an output coupled to an input of the current gain device. The second current source provides a current which is a fraction of the reference current. A switching transistor has an output electrode coupled to: (1) an input of the current gain device; and, (2) an output of the second current source.

Abstract: An IGBT has striped cell with source stripes 2a, 2b continuous or segmented along the length of the base stripe 3. The opposite stripes are periodically connected together by the N+ contact regions 20 to provide channel resistance along the width of the source stripes 2a, 2b. For continuous stripes the resistance between two sequential contact areas 20a, 20b is greatest in the middle and current concentrates near the source contact regions 20. The wider the spacing between the contacts 20, the larger the resistive drop to the midpoint between two N+ contacts 20.

Abstract: An IGBT has a thick buffer region with increased doping to improve self-clamped inductive switching and device manufacture. A planar or trench gate IGBT has a buffer layer more than 25 microns thick. The buffer layer is doped high enough so that its carriers are more numerous than minority carriers, particularly at the transition between the N buffer & N drift region.

Abstract: A delay lock loop circuit includes a forward delay circuit receiving a reference clock signal and issuing a first delayed clock signal. The forward delay circuit adjustably shifts in time the first delayed clock signal relative to the reference clock signal. A fixed delay circuit receives the first delayed clock signal and issues a second delayed clock signal. A feedback delay circuit receives a selected one of the first delayed and the second delayed clock signals, and issues a feedback clock signal. The feedback clock signal is shifted in time relative to the selected one of the first delayed and the second delayed clock signals.

Abstract: An integrated lipstick and lip pencil comprises a lipstick part for painting a user's lips with a lipstick of a prescribed color, a lip pencil part for penciling a lip line using a lip pencil, and a coupling part for coupling the lipstick part and the lip pencil part to combine them into one body.

Abstract: A delay lock loop circuit for aligning in time a reference clock signal with an internal feedback clock signal includes a forward delay circuit that receives the reference clock signal. The forward delay circuit includes a forward delay line having a plurality of electrically interconnected delay blocks. Each of the delay blocks includes a predetermined number of electrically interconnected delay units. Disabling means deactivate the one or more delay blocks when the delay blocks are not needed in order to time align the reference clock signal and the internal feedback clock signal.

Abstract: A method for removal of post reactive ion etch by-product from a semiconductor wafer surface or microelectronic composite structure comprising: supplying a reducing gas plasma incorporating a forming gas mixture selected from the group consisting of a mixture of N2/H2 or a mixture of NH3/H2 into a vacuum chamber in which a semiconductor wafer surface or a microelectronic composite structure is supported to form a post-RIE polymer material by-product on the composite structure without significant removal of an organic, low K material which has also been exposed to the reducing gas plasma; and removing the post-RIE polymer material by-product with a wet clean.

Abstract: A more robust mechanical connection is provided between a semiconductor device and the device package by adding one or more bumps to the gate connection without adding more gate pad area. A nonconductive layer covers the area around the gate pad and extends over the source area. One or more bumps fabricated on the nonconductive layer provide mechanical strength and support to the gate pad connection. The added bumps are not electrically connected to either the gate or the source. The package connections must be altered, both to fit the added bumps on the control gate, and to connect with fewer bumps on the source.

Abstract: A method for animating a 3-D model of a person's face is disclosed. The 3-D face model carries both the geometry (shape) and the texture (color) characteristics of the person's face. The shape of the face model is represented via a 3-D triangular mesh (geometry mesh), while the texture of the face model is represented via a 2-D composite image (texture image). A separate 3-D triangular mesh, called the shape mesh, is used to animate the nodes of the geometry mesh: Each triangle of the shape mesh controls the motion of a plurality of nodes of the geometry mesh that are connected to it. Thus, by moving the nodes of the shape mesh, which are small in number, the nodes of the geometry mesh, which can be very large in number, are animated realistically. The nodes of the shape mesh can be moved directly or indirectly. In the indirect method, the nodes of the shape mesh are moved in accordance with the so-called facial action values, which are even smaller in number than the nodes of the shape mesh.

Abstract: A method for fabricating a self-aligned contact in an integrated circuit includes defining first spacer layers over the sidewalls of a pair of wordline stacks. An oxide layer is deposited over the tops of the wordline stacks, the first spacer layers and a surface of the substrate disposed between the first spacer layers. The oxide layer is removed from the first spacer layers, thereby forming a remaining oxide layer that covers the surface of the substrate disposed between the first spacer layers. Second spacer layers are formed over the first spacer layers, and which cover respective portions of the remaining oxide layer. The remaining oxide layer is removed to thereby form undercut regions. The undercut regions are substantially filled with contact material during formation of the contact.

Abstract: An LDMOS device is made on a semiconductor substrate 112. It has an N+ source and drain regions 120, 132 are formed within a P well region 122. An interlevel dielectric layer 140 encapsulates biased charge control electrodes 142a and they control the electric field within the area of the drift region 14 between P-base 122 and the N drain region 132 to increase the reverse breakdown voltage of the device. This permits the user to more heavily dope the drift region and achieve a lower on resistance.

Abstract: Flash EEPROM cells are erased and recovered to a common threshold voltage by a two step process. First, the cells are erased. Second, the fixed (control) gates are set at a voltage of the same polarity as the programming voltage and at a magnitude of about half the programming voltage. The source is allowed to float and the drain (bitline) and body are set at a low level and at a polarity opposite to the programming voltage polarity.

Abstract: A delay lock loop circuit includes a forward delay circuit having a plurality of delay elements. Each delay element has a delay time of one unit delay time. The forward delay circuit and each of the delay elements are powered by a supply voltage. The supply voltage is set to thereby set the duration of a unit delay time. Moreover, a feedback delay circuit is provided in order to cause a feedback delay time being substantially equal to a propagation delay of the IC. As the operating conditions of IC change, and the propagation delay thereof increases or decreases, the feedback delay time changes accordingly, and thus the delay caused by forward delay circuit tracks the change in the propagation delay of the IC.

Abstract: The cellular structure of the power device includes a substrate that has a highly doped drain region. Over the substrate there is a more lightly doped epitaxial layer of the same doping. Above the epitaxial layer is a well region formed of an opposite type doping. Covering the wells is an upper source layer of the first conductivity type that is heavily doped. The trench structure includes a sidewall oxide or other suitable insulating material that covers the sidewalls of the trench. The bottom of the trench is filled with a doped polysilicon shield. An interlevel dielectric such as silicon nitride covers the shield. The gate region is formed by another layer of doped polysilicon. A second interlevel dielectric, typically borophosphosilicate glass (BPSG) covers the gate. In operation, current flows vertically between the source and the drain through a channel in the well when a suitable voltage is applied to the gate.

Abstract: A method for forming trenches in a device layer disposed on a silicon semiconductor substrate comprises: covering the device layer with an etch resistant masking layer to define at least two trench regions; removing semiconductor material from the exposed trench regions by applying an etching agent that selectively etches the semiconductor substrate with respect to the trench masking layer, thereby forming at least two trenches each comprising a floor and sidewalls; and, during the removal of semiconductor material, exposing the sidewalls to a passivating agent in increasing amounts, thereby passivating the sidewalls while reducing lateral etching of semiconductor material from them.

Abstract: The present invention relates to a weapon safeguarding system with a first contact-sensitive user interface for receiving use data characterizing a user. In this connection the first contact-sensitive use interface is arranged in a contact region of a weapon which is contacted by the user with a view to firing a shot. The weapon safeguarding system further comprises a control device which comprises an input unit for receiving the user data, a computer unit for verifying the user data and an output unit. In the case of a successful verification of the user data, which indicates that the user is a user who is authorized for use, the output unit outputs a release signal in order to release a discharging mechanism of the weapon.

Abstract: A power MOS device that has increased channel width comprises a semiconductor substrate and a doped upper layer of a first conduction type disposed on the substrate. The upper layer comprises a plurality of doped well regions of a second, opposite conduction type and a plurality of heavily doped source regions of the first conduction type at an etched upper surface of the upper layer that comprises parallel corrugations disposed transversely to the source regions. A gate that separates one source region from another comprises an insulating layer and a conductive material. The corrugations provide an increase in width of a channel underlying the gate and the well and source regions.

Abstract: A process for constructing a trench MOS-gated device includes: forming in a semiconductor substrate an extended trench that comprises an upper segment and a bottom segment, wherein the bottom segment has a lesser width relative to a greater width of the trench upper segment and extends to a depth corresponding to the total depth of the extended trench. The bottom segment of the trench is substantially filled with dielectric material. The trench upper segment has a floor and sidewalls comprising dielectric material and is substantially filled with a conductive material to form a gate region. A heavily doped source region of the first conduction type and a heavily doped body region of the second conduction type are formed in a surface well region on the side of the extended trench opposite an extended doped zone.